公开(公告)号：US06901653B2

公开(公告)日：2005-06-07

申请号：US10115414

申请日：2002-04-02

申请人： Richard Hsiao ,  Prakash Kasiraj ,  Quang Le ,  Paul Phong Nguyen ,  Son Van Nguyen ,  Denny D. Tang ,  Patrick Rush Webb

发明人： Richard Hsiao ,  Prakash Kasiraj ,  Quang Le ,  Paul Phong Nguyen ,  Son Van Nguyen ,  Denny D. Tang ,  Patrick Rush Webb

IPC分类号： G11B5/17 ,  G11B5/31

CPC分类号： G11B5/3163 ,  G11B5/17 ,  G11B5/313 ,  Y10T29/49043 ,  Y10T29/49048 ,  Y10T29/4906 ,  Y10T29/49064 ,  Y10T29/49073 ,  Y10T29/49165

摘要： A Damascene process is provided for manufacturing a coil structure for a magnetic head. During the manufacturing process, an insulating layer is initially deposited after which a photoresist layer is deposited. A silicon dielectric layer is then deposited on the photoresist layer. After masking the silicon dielectric layer, at least one channel is etched in the photoresist layer and the silicon dielectric layer. Then, a conductive seed layer is deposited in the at least one channel. The at least one channel is then ready to be filled with a conductive material and chemically/mechanically polished to define a coil structure.

摘要翻译： 提供一种用于制造用于磁头的线圈结构的镶嵌工艺。 在制造过程中，首先沉积绝缘层，之后沉积光致抗蚀剂层。 然后在光致抗蚀剂层上沉积硅介电层。 在掩蔽硅介电层之后，在光致抗蚀剂层和硅介电层中蚀刻至少一个通道。 然后，在至少一个通道中沉积导电种子层。 然后至少一个通道准备用导电材料填充并进行化学/机械抛光以限定线圈结构。

公开(公告)号：US06878620B2

公开(公告)日：2005-04-12

申请号：US10293543

申请日：2002-11-12

申请人： Son Van Nguyen ,  Li-Qun Xia ,  Srinivas D. Nemani

发明人： Son Van Nguyen ,  Li-Qun Xia ,  Srinivas D. Nemani

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76844 ,  H01L21/76829 ,  H01L21/76831

摘要： Methods and apparatus for protecting the dielectric layer sidewalls of openings, such as vias and trenches, in semiconductor substrates are provided. A pre-liner and a liner are deposited over the sidewalls of the openings as part of integrated processing sequences that either do not remove the photoresist until subsequent processing or remove the photoresist with a plasma etch that does not contaminate the sidewalls of the openings.

摘要翻译： 提供了用于保护半导体衬底中诸如通路和沟槽之类的开口的电介质层侧壁的方法和装置。 预先衬里和衬垫沉积在开口的侧壁上，作为集成处理顺序的一部分，其不会除去光致抗蚀剂，直到后续处理或用不污染开口侧壁的等离子体蚀刻去除光致抗蚀剂。

公开(公告)号：US06399976B1

公开(公告)日：2002-06-04

申请号：US08467353

申请日：1995-06-06

申请人： Peter John Geiss ,  Howard Smith Landis ,  Son Van Nguyen

发明人： Peter John Geiss ,  Howard Smith Landis ,  Son Van Nguyen

IPC分类号： H01L27108

CPC分类号： H01L27/10861 ,  H01L29/66181

摘要： Crystal lattice dislocations in material surrounding trench capacitors and other trench structures are avoided by alteration of stresses such as decreasing compressive stresses and/or development of persistent tensile forces within material deposited in the trench and thus at the material interface formed by the trench. Such alteration of stresses is achieved by volume reduction of a film deposited in the trench. The material is preferably a hydrogenated nitride of silicon, boron or silicon-carbon alloy which may be reduced in volume by partial or substantially complete dehydrogenation during subsequent heat treatment at temperatures where the film will exhibit substantial creep resistance. The amount of volume reduction can be closely controlled by control of concentration of hydrogen or other gas or volatile material in the film. Further fine adjustment of stresses can be achieved in combination with this mechanism by volume reduction of other materials which may be used, in part, to confine the film through other mechanisms such as annealing.

摘要翻译： 在沟槽电容器和其他沟槽结构周围的材料中的晶格位错通过改变应力来避免，例如减小压缩应力和/或沉积在沟槽中的材料内部以及因此在由沟槽形成的材料界面处的持续张力的变化。 通过在沟槽中沉积的膜的体积减小来实现应力的这种改变。 该材料优选是硅，硼或硅 - 碳合金的氢化氮化物，其可以在随后的热处理期间通过部分或基本上完全脱氢体积减小，其中该膜将呈现显着的耐蠕变性。 可以通过控制膜中的氢或其它气体或挥发性物质的浓度来严格控制体积减少的量。 通过其它材料的体积减少，可以通过结合该机理来实现应力的进一步细微调节，其它材料可以部分地通过其它机制例如退火来限制膜。

公开(公告)号：US5753948A

公开(公告)日：1998-05-19

申请号：US752137

申请日：1996-11-19

申请人： Son Van Nguyen ,  Matthias Ilg ,  Kevin J. Uram

发明人： Son Van Nguyen ,  Matthias Ilg ,  Kevin J. Uram

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/72

CPC分类号： H01L27/1085 ,  H01L28/87

摘要： Capacitor storage charge can be increased by increasing storage node area. A high aspect surface ratio stack capacitor is produced without increasing overall cell dimensions. The node is formed with layers of low doped and high doped concentration borophosphosilicate glass which is deposited by a single process step with precise nanometer dimensions, are selectively etched so that either doped or undoped layers will have a higher etch rate. This etching creates finger-like projections in the node, which provide for greater surface area using a very simplified process requiring fewer processing steps.

公开(公告)号：US09502288B2

公开(公告)日：2016-11-22

申请号：US13420728

申请日：2012-03-15

申请人： Son Van Nguyen ,  Alfred Grill ,  Thomas J. Haigh, Jr. ,  Hosadurga Shobha ,  Tuan A. Vo

发明人： Son Van Nguyen ,  Alfred Grill ,  Thomas J. Haigh, Jr. ,  Hosadurga Shobha ,  Tuan A. Vo

IPC分类号： H05K3/02 ,  H05K3/10 ,  H01L21/768

CPC分类号： H01L21/76849 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76867

摘要： An interconnect structure is provided that has improved electromigration resistance as well as methods of forming such an interconnect structure. The interconnect structure includes a composite M-MOx cap located at least on the upper surface of the Cu-containing material within the at least one opening. The composite M-MOx cap includes an upper region that is composed of the metal having a higher affinity for oxygen than copper and copper oxide and a lower region that is composed of a non-stoichiometric oxide of said metal.

摘要翻译： 提供了具有改进的电迁移阻力的互连结构以及形成这种互连结构的方法。 互连结构包括至少位于至少一个开口内的含Cu材料的上表面上的复合M-MOx帽。 复合M-MOx帽包括由与氧和氧化铜相比具有比氧更高的亲和性的金属构成的上部区域和由所述金属的非化学计量氧化物构成的下部区域。

公开(公告)号：US20090305514A1

公开(公告)日：2009-12-10

申请号：US12506954

申请日：2009-07-21

申请人： Francimar Campana Schmitt ,  Li-Qun Xia ,  Son Van Nguyen ,  Shankar Venkataraman

发明人： Francimar Campana Schmitt ,  Li-Qun Xia ,  Son Van Nguyen ,  Shankar Venkataraman

IPC分类号： H01L21/316 ,  H01L21/314

CPC分类号： H01L21/76835 ,  C23C16/0272 ,  C23C16/30 ,  C23C16/325 ,  C23C16/505 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/02351 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/3121 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/7681 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832

摘要： Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including depositing a barrier layer on the substrate, wherein the barrier layer comprises silicon and carbon and has a dielectric constant less than 4, depositing a dielectric initiation layer adjacent the barrier layer, and depositing a first dielectric layer adjacent the dielectric initiation layer, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less.

摘要翻译： 提供了用于处理用于沉积在两个低k电介质层之间具有低介电常数的粘合层的衬底的方法。 一方面，本发明提供了一种处理衬底的方法，包括在衬底上沉积阻挡层，其中阻挡层包括硅和碳并具有小于4的介电常数，沉积与阻挡层相邻的电介质起始层，以及 沉积与电介质起始层相邻的第一电介质层，其中介电层包括硅，氧和碳并且具有约3或更小的介电常数。

公开(公告)号：US07563728B2

公开(公告)日：2009-07-21

申请号：US11678752

申请日：2007-02-26

申请人： Francimar Campana Schmitt ,  Li-Qun Xia ,  Son Van Nguyen ,  Shankar Venkataraman

发明人： Francimar Campana Schmitt ,  Li-Qun Xia ,  Son Van Nguyen ,  Shankar Venkataraman

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/76835 ,  C23C16/0272 ,  C23C16/30 ,  C23C16/325 ,  C23C16/505 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/02351 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/3121 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/7681 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832

摘要： Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including depositing a barrier layer on the substrate, wherein the barrier layer comprises silicon and carbon and has a dielectric constant less than 4, depositing a dielectric initiation layer adjacent the barrier layer, and depositing a first dielectric layer adjacent the dielectric initiation layer, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less.

摘要翻译： 提供了用于处理用于沉积在两个低k电介质层之间具有低介电常数的粘合层的衬底的方法。 一方面，本发明提供了一种处理衬底的方法，包括在衬底上沉积阻挡层，其中阻挡层包括硅和碳并具有小于4的介电常数，沉积与阻挡层相邻的电介质起始层，以及 沉积与电介质起始层相邻的第一电介质层，其中介电层包括硅，氧和碳并且具有约3或更小的介电常数。

公开(公告)号：US20090181178A1

公开(公告)日：2009-07-16

申请号：US12355316

申请日：2009-01-16

申请人： Daniel C. Edelstein ,  Stephen M. Gates ,  Alfred Grill ,  Michael Lane ,  Qinghuang Lin ,  Robert D. Miller ,  Deborah A. Neumayer ,  Son Van Nguyen

发明人： Daniel C. Edelstein ,  Stephen M. Gates ,  Alfred Grill ,  Michael Lane ,  Qinghuang Lin ,  Robert D. Miller ,  Deborah A. Neumayer ,  Son Van Nguyen

IPC分类号： C23C16/22

CPC分类号： H01L31/103 ,  Y10T428/31663

摘要： A low-k dielectric material with increased cohesive strength for use in electronic structures including interconnect and sensing structures is provided that includes atoms of Si, C, O, and H in which a fraction of the C atoms are bonded as Si—CH3 functional groups, and another fraction of the C atoms are bonded as Si—R—Si, wherein R is phenyl, —[CH2]n— where n is greater than or equal to 1, HC═CH, C═CH2, C═C or a [S]n linkage, where n is a defined above.

摘要翻译： 提供了一种用于包括互连和感测结构的电子结构中具有增强的内聚强度的低k电介质材料，其包括其中一部分C原子键合为Si-CH 3官能团的Si，C，O和H的原子 ，另一部分C原子键合为Si-R-Si，其中R为苯基， - [CH2] n-，其中n大于或等于1，HC-CH，C-CH2，CC或[ S] n连接，其中n是上面定义的。

公开(公告)号：US07485582B2

公开(公告)日：2009-02-03

申请号：US12016594

申请日：2008-01-18

申请人： Son Van Nguyen ,  Michael Lane ,  Stephen M. Gates ,  Xiao H. Liu ,  Vincent J. McGahay ,  Sanjay C. Mehta ,  Thomas M. Shaw

发明人： Son Van Nguyen ,  Michael Lane ,  Stephen M. Gates ,  Xiao H. Liu ,  Vincent J. McGahay ,  Sanjay C. Mehta ,  Thomas M. Shaw

IPC分类号： H01L21/44

CPC分类号： H01L21/3148 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/3122 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76832 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/24802 ,  H01L2924/00

摘要： The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric material and an upper region comprising atoms of Si, C and H located above the hermetic oxide material. The present invention also provides a method of fabricating the inventive hardmask as well as a method to form an interconnect structure containing the same.

摘要翻译： 本发明提供了一种硬掩模，其位于具有嵌入其中的至少一个导电特征的低k电介质材料的表面上。 硬掩模包括邻近低k电介质材料的气密氧化物材料的下部区域，以及包含位于密封氧化物材料上方的Si，C和H原子的上部区域。 本发明还提供了制造本发明的硬掩模的方法以及形成包含该硬掩模的互连结构的方法。

公开(公告)号：US20080286494A1

公开(公告)日：2008-11-20

申请号：US12044334

申请日：2008-03-07

申请人： Christos Dimitrios Dimitrakopoulos ,  Stephen McConnell Gates ,  Alfred Grill ,  Michael Wayne Lane ,  Eric Gerhard Liniger ,  Xiao Hu Liu ,  Son Van Nguyen ,  Deborah Ann Neumayer ,  Thomas McCarroll Shaw

发明人： Christos Dimitrios Dimitrakopoulos ,  Stephen McConnell Gates ,  Alfred Grill ,  Michael Wayne Lane ,  Eric Gerhard Liniger ,  Xiao Hu Liu ,  Son Van Nguyen ,  Deborah Ann Neumayer ,  Thomas McCarroll Shaw

IPC分类号： B01J19/08 ,  C23C16/44

CPC分类号： H01L21/76834 ,  C23C16/30 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  Y10T428/249953 ,  Y10T428/249969 ,  Y10T428/249979

摘要： A method for forming a ultralow dielectric constant layer with controlled biaxial stress is described incorporating the steps of forming a layer containing Si, C, O and H by one of PECVD and spin-on coating and curing the film in an environment containing very low concentrations of oxygen and water each less than 10 ppm. A material is also described by using the method with a dielectric constant of not more than 2.8. The invention overcomes the problem of forming films with low biaxial stress less than 46 MPa.