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23 条记录 (耗时 0.024 秒)

    Single bit array edges
    11.
    发明授权
    Single bit array edges 有权
    单位阵列边缘

    公开(公告)号：US06493261B1

    公开(公告)日：2002-12-10

    申请号：US09795865

    申请日：2001-02-28

    申请人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Ravi Sunkavalli ,  Narbeh Derhacobian ,  Michael A. Van Buskirk

    发明人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Ravi Sunkavalli ,  Narbeh Derhacobian ,  Michael A. Van Buskirk

    IPC分类号： G11C1604

    CPC分类号： G11C16/3409 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/344 ,  G11C16/3445 ,  H01L27/115

    摘要： Dummy columns of memory cells formed during fabrication outside edge columns are connected to the actual used memory cells of sectors or the like. The columns of dummy memory cells are compensated by floating the dummy memory cells during normal programming and erase cycles, or alternatively, by programming and erasing the dummy memory cells along with the actual used memory cells in the sector. By treating the dummy memory cells similar to the actual used cells, charge that leaks into the dummy cells during fabrication and normal operation that has deleterious effects at higher stress temperatures and/or due to the longevity of customer operation is substantially eliminated.

    摘要翻译： 在制造外边缘列时形成的存储单元的虚拟柱被连接到扇区等的实际使用的存储单元。 虚拟存储单元的列通过在正常编程和擦除周期期间浮置伪存储单元来补偿，或者通过编程和擦除虚存储单元以及扇区中的实际使用的存储单元来补偿。 通过处理类似于实际使用的电池的虚拟存储器单元，在制造和正常操作期间泄漏到虚拟电池中的电荷在较高应力温度和/或由于客户操作的寿命而具有有害影响的基本上被消除。

    Method of determining charge loss activation energy of a memory array
    12.
    发明授权
    Method of determining charge loss activation energy of a memory array 失效
    确定存储器阵列的电荷损耗激活能的方法

    公开(公告)号：US06813752B1

    公开(公告)日：2004-11-02

    申请号：US10306667

    申请日：2002-11-26

    申请人： Edward Hsia ,  Darlene G. Hamilton ,  Wei Zheng ,  Mark W. Randolph ,  Kulachet Tanpairoj

    发明人： Edward Hsia ,  Darlene G. Hamilton ,  Wei Zheng ,  Mark W. Randolph ,  Kulachet Tanpairoj

    IPC分类号： G06F1750

    CPC分类号： G11C29/50 ,  G11C16/04

    摘要： A method of determining charge loss activation for a memory array. Memory arrays are programmed with a pattern for testing charge loss. Then, respective bake times are calculated for the memory arrays to experience a given amount of charge loss at their respective bake temperatures. Then, charge loss activation energy is calculated, based on the respective bake times. In one version, the memory arrays are cycled by repeatedly erasing and reprogramming them before baking. In another embodiment, various regions of the memory arrays are programmed to a plurality of distinct delta threshold voltages before baking.

    摘要翻译： 确定存储器阵列的电荷损失激活的方法。 存储器阵列被编程用于测试电荷损失的模式。 然后，对于存储器阵列计算各自的烘烤时间，以在其各自的烘烤温度下经历给定量的电荷损失。 然后，基于相应的烘烤时间计算电荷损失激活能。 在一个版本中，通过在烘烤之前重复擦除和重新编程它们来循环存储器阵列。 在另一个实施例中，存储器阵列的各个区域在烘烤之前被编程为多个不同的增量阈值电压。

    Tailored erase method using higher program VT and higher negative gate erase
    13.
    发明授权
    Tailored erase method using higher program VT and higher negative gate erase 有权
    使用更高程序VT和更高的负栅极擦除进行定制擦除方法

    公开(公告)号：US06442074B1

    公开(公告)日：2002-08-27

    申请号：US09795854

    申请日：2001-02-28

    申请人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Ravi Sunkavalli ,  Narbeh Derhacobian

    发明人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Ravi Sunkavalli ,  Narbeh Derhacobian

    IPC分类号： G11C1604

    CPC分类号： G11C16/3409 ,  G11C16/04 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/3404 ,  G11C16/344 ,  G11C16/3445 ,  G11C29/50

    摘要： A method and system for programming and erasing the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT and an erase pulse that provides a substantially high electric field to each I/O in a sector one at a time. After the first erase pulse, the erase verify routine is performed on all the IO's together. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. This erase pulse that provides a substantially high electric field is selected to erase band to band currents for the entire array that are larger than can be supplied by drain pumps.

    摘要翻译： 用于编程和擦除双位存储器单元的存储器阵列的正常位的方法和系统通过以基本上高的delta VT和擦除脉冲进行编程来实现，该擦除脉冲为扇区1中的每个I / O提供基本上高的电场 一次 在第一个擦除脉冲之后，擦除验证程序在所有IO上一起执行。 基本上更高的VT确保存储器阵列将维持编程数据并且在相当长的一段时间内在较高的温度应力和/或客户操作之后一致地擦除数据。 选择提供基本上高的电场的擦除脉冲，以消除整个阵列的频带电流，其大于由排水泵提供的频带电流。

    FAST SINGLE PHASE PROGRAM ALGORITHM FOR QUADBIT
    14.
    发明申请
    FAST SINGLE PHASE PROGRAM ALGORITHM FOR QUADBIT 有权
    用于四边形的快速单相程序算法

    公开(公告)号：US20090103357A1

    公开(公告)日：2009-04-23

    申请号：US11874076

    申请日：2007-10-17

    申请人： Darlene Hamilton ,  Fatima Bathul ,  Kulachet Tanpairoj ,  Ou Li

    发明人： Darlene Hamilton ,  Fatima Bathul ,  Kulachet Tanpairoj ,  Ou Li

    IPC分类号： G11C16/10

    CPC分类号： G11C16/10 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/3418 ,  G11C2211/5621

    摘要： Methods of rapidly programming a wordline of multi-level flash memory cells comprising memory cell element-pairs having three or more data levels per bit or element corresponding to three or more threshold voltages are provided. An interactive program algorithm rapidly programs the elements of the wordline of memory cells in a learn phase and a single core programming phase. In one embodiment, each wordline comprises learn element-pairs first programmed to provide learn drain voltages for programming core element-pairs along the wordline having the same program pattern of data levels. A set comprising one or more program patterns is chosen to correspond with each program level used on the wordline. The learn element-pairs are programmed to determine a learned program drain voltage for each program level. This learned program drain voltage essentially provides a wordline and program level specific program characterization of the Vd required for the remaining elements of that wordline.

    摘要翻译： 提供了快速编程多级闪存单元的字线的方法，其包括每位具有三个或更多个数据级或对应于三个或更多阈值电压的元件的存储单元元件对。 交互式程序算法在学习阶段和单个核心编程阶段快速地对存储器单元的字线的元素进行编程。 在一个实施例中，每个字线包括首先被编程为提供学习漏极电压的学习元件对，用于沿着具有相同数据级别的程序模式的字线编程核心元件对。 选择包括一个或多个节目模式的集合以对应于字线上使用的每个节目级别。 学习元件对被编程以确定每个程序级的学习程序漏极电压。 这个学习的程序漏极电压基本上提供了字线和程序级特定程序表征该字母的剩余元件所需的Vd。

    Experience count dependent program algorithm for flash memory
    19.
    发明授权
    Experience count dependent program algorithm for flash memory 有权
    体验闪存的计数依赖程序算法

    公开(公告)号：US08750045B2

    公开(公告)日：2014-06-10

    申请号：US13560896

    申请日：2012-07-27

    申请人： Jianmin Huang ,  Kulachet Tanpairoj ,  Chris Nga Yee Avila ,  Gautam Ashok Dusija

    发明人： Jianmin Huang ,  Kulachet Tanpairoj ,  Chris Nga Yee Avila ,  Gautam Ashok Dusija

    IPC分类号： G11C16/06 ,  G11C16/10

    CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/3481 ,  G11C16/3495

    摘要： In a non-volatile memory device, the parameters used in write and erase operation are varied based upon device age. For example, in a programming operation using a staircase waveform, the amplitude of the initial pulse can be adjusted based upon the number of erase-program cycles (hot count) of the block containing the selected physical page for the write. This arrangement can preserve performance for relatively fresh devices, while extending life as a devices ages by using gentler waveforms as the device ages.

    摘要翻译： 在非易失性存储器件中，用于写入和擦除操作的参数根据器件寿命而变化。 例如，在使用阶梯波形的编程操作中，可以根据包含所选择的用于写入的物理页的块的擦除程序周期（热计数）的次数来调整初始脉冲的幅度。 这种布置可以保持相对新鲜的设备的性能，同时通过在设备老化时通过使用温和波形来延长设备的使用寿命。