公开(公告)号：US20140361387A1

公开(公告)日：2014-12-11

申请号：US13910133

申请日：2013-06-05

申请人： Thorsten Meyer ,  Gerald Ofner ,  Christian Mueller ,  Reinhard Mahnkopf ,  Christian Geissler ,  Andreas Augustin

发明人： Thorsten Meyer ,  Gerald Ofner ,  Christian Mueller ,  Reinhard Mahnkopf ,  Christian Geissler ,  Andreas Augustin

IPC分类号： B81B7/00 ,  B81C1/00

CPC分类号： B81B7/0077 ,  B81B7/007 ,  B81B2207/012 ,  B81B2207/095 ,  B81C1/00333 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2924/1431 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A chip arrangement may include: a mold compound; and a microelectromechanical systems device at least partially embedded in the mold compound.

摘要翻译： 芯片布置可以包括：模具化合物; 以及至少部分地嵌入模具化合物中的微机电系统装置。

公开(公告)号：US20140197530A1

公开(公告)日：2014-07-17

申请号：US13739045

申请日：2013-01-11

申请人： Thorsten Meyer ,  Sven Albers ,  Christian Geissler ,  Andreas Wolter ,  Markus Brunnbauer ,  David O'Sullivan ,  Frank Zudock ,  Jan Proschwitz

发明人： Thorsten Meyer ,  Sven Albers ,  Christian Geissler ,  Andreas Wolter ,  Markus Brunnbauer ,  David O'Sullivan ,  Frank Zudock ,  Jan Proschwitz

IPC分类号： H01L23/29 ,  H01L21/56

CPC分类号： H01L23/315 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/562 ,  H01L24/19 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor device is described having at least one semiconductor chip, the chip having an active area on a top side thereof, the active area formed at least in part of low-k material, said low-k material defining a low-k subarea of said active area; an embedding material, in which said at least one semiconductor chip is embedded, at least part of the embedding material forming a coplanar area with said active area; at least one contact area within the low-k subarea; a redistribution layer on the coplanar area, the redistribution layer connected to said contact areas; at least one first-level interconnect, located outside said low-k subarea, the first-level interconnect electrically connected to at least one of said contact areas via the redistribution layer.

摘要翻译： 描述了半导体器件，其具有至少一个半导体芯片，该芯片在其顶侧具有有源区，至少部分形成在低k材料上的有源区，所述低k材料限定低k分区 说活跃区; 嵌入材料，其中所述至少一个半导体芯片被嵌入，所述嵌入材料的至少一部分与所述有源区域形成共面区域; 低k子区域内的至少一个接触区域; 在共面区域上的再分配层，再分配层连接到所述接触区域; 位于所述低k子区域外的至少一个第一级互连，所述第一级互连经由再分配层电连接到所述接触区域中的至少一个。

公开(公告)号：US08415803B2

公开(公告)日：2013-04-09

申请号：US12871939

申请日：2010-08-31

申请人： Thorsten Meyer ,  Gottfried Beer ,  Christian Geissler ,  Thomas Ort ,  Klaus Pressel ,  Bernd Waidhas ,  Andreas Wolter

发明人： Thorsten Meyer ,  Gottfried Beer ,  Christian Geissler ,  Thomas Ort ,  Klaus Pressel ,  Bernd Waidhas ,  Andreas Wolter

IPC分类号： H01L23/48 ,  H01L21/768

摘要： A method and a system for routing electrical connections are disclosed. A semiconductor device includes a first semiconductor chip and a routing plane having a plurality of routing lines. A first connecting line is electrically coupled to the first semiconductor chip and one of the plurality of routing lines and a second connecting line is electrically coupled to the one of the plurality of routing lines and to one of a second semiconductor chip or a first external contact element.

公开(公告)号：US20070080390A1

公开(公告)日：2007-04-12

申请号：US11431265

申请日：2006-05-10

申请人： Christian Geissler ,  Franz Schuler ,  Danny Shum

发明人： Christian Geissler ,  Franz Schuler ,  Danny Shum

IPC分类号： H01L29/788

CPC分类号： G11C16/0416

摘要： An integrated memory transistor and a memory unit including a plurality of integrated memory transistors is disclosed. Generally, the integrated memory transistor includes an electron source, a channel region, a control region, a charge storage region, a source-side pocket doping region, and a drain-side pocket doping region. The electron source is operable to transport electrons to the channel region when the integrated memory transistor operates in a read mode. Further, the electron source includes a drain terminal region and a source terminal region. The channel region is arranged between the drain terminal region and source terminal region. The charge storage region is arranged between the control region and the channel region. The source-side doping region is arranged nearer to the source terminal region than to the drain terminal region. The drain-side pocket doping region is arranged asymmetrical to the source-side pocket doping region.

摘要翻译： 公开了一种集成存储晶体管和包括多个集成存储晶体管的存储单元。 通常，集成存储晶体管包括电子源，沟道区，控制区，电荷存储区，源极侧掺杂区和漏极侧杂质掺杂区。 当集成存储晶体管以读取模式工作时，电子源可操作以将电子传输到沟道区域。 此外，电子源包括漏极端子区域和源极端子区域。 沟道区域布置在漏极端子区域和源极端子区域之间。 电荷存储区域设置在控制区域和沟道区域之间。 源极侧掺杂区域比漏极端子区域更靠近源极端子区域。 漏极侧杂质掺杂区域与源极侧掺杂区域不对称地布置。

公开(公告)号：US20150262866A1

公开(公告)日：2015-09-17

申请号：US14205093

申请日：2014-03-11

申请人： Thorsten Meyer ,  Gerald Ofner ,  Teodora Ossiander ,  Frank Zudock ,  Christian Geissler

发明人： Thorsten Meyer ,  Gerald Ofner ,  Teodora Ossiander ,  Frank Zudock ,  Christian Geissler

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/532 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/02 ,  H01L23/528

CPC分类号： H01L24/11 ,  H01L21/02282 ,  H01L21/02318 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76871 ,  H01L23/525 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0361 ,  H01L2224/0381 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/211 ,  H01L2224/8112 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/821 ,  H01L2224/82105 ,  H01L2224/94 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/143 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2224/03

摘要： Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer. The method may further include laminating a dielectric material on the passivation layer to form a dielectric layer and selectively removing dielectric material to form voids in the dielectric layer. These voids may reveal portions of the passivation layer disposed over the metal conductors. The method may then involve removing the portions of the passivation layer to reveal the metal conductors. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例涉及组装集成电路封装的方法。 在实施例中，该方法可以包括提供具有未图案化钝化层的晶片以防止嵌入晶片中的金属导体的腐蚀。 该方法还可以包括将绝缘材料层压在钝化层上以形成电介质层，并选择性地去除电介质材料以在电介质层中形成空隙。 这些空隙可以露出设置在金属导体上的钝化层的部分。 该方法可以包括去除钝化层的部分以露出金属导体。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20150091167A1

公开(公告)日：2015-04-02

申请号：US14039157

申请日：2013-09-27

申请人： Christian Geissler ,  Thorsten Meyer ,  Gerald Ofner ,  Reinhard Mahnkopf ,  Andreas Augustin ,  Christian Mueller

发明人： Christian Geissler ,  Thorsten Meyer ,  Gerald Ofner ,  Reinhard Mahnkopf ,  Andreas Augustin ,  Christian Mueller

IPC分类号： B81C1/00 ,  B81B7/00

CPC分类号： B81C1/00666 ,  B81B7/0054 ,  B81C1/00261 ,  B81C1/00349 ,  B81C2203/0136 ,  B81C2203/0154 ,  H01L21/568 ,  H01L23/3135 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/24137 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/73207 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73277 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Stress buffer layers for integrated microelectromechanical systems (MEMS) are described. For example, a semiconductor package includes a substrate having first and second surfaces, the second surface having an array of external conductive contacts. A microelectromechanical system (MEMS) component is disposed above the first surface of the substrate. A buffer layer is disposed above the MEMS component, the buffer layer having a first Young's modulus. A mold compound is disposed above the buffer layer, the mold compound having a second Young's modulus higher than the first Young's modulus.

公开(公告)号：US09056763B2

公开(公告)日：2015-06-16

申请号：US14039157

申请日：2013-09-27

申请人： Christian Geissler ,  Thorsten Meyer ,  Gerald Ofner ,  Reinhard Mahnkopf ,  Andreas Augustin ,  Christian Mueller

发明人： Christian Geissler ,  Thorsten Meyer ,  Gerald Ofner ,  Reinhard Mahnkopf ,  Andreas Augustin ,  Christian Mueller

IPC分类号： H01L23/02 ,  B81C1/00 ,  B81B7/00

CPC分类号： B81C1/00666 ,  B81B7/0054 ,  B81C1/00261 ,  B81C1/00349 ,  B81C2203/0136 ,  B81C2203/0154 ,  H01L21/568 ,  H01L23/3135 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/24137 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/73207 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73277 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Stress buffer layers for integrated microelectromechanical systems (MEMS) are described. For example, a semiconductor package includes a substrate having first and second surfaces, the second surface having an array of external conductive contacts. A microelectromechanical system (MEMS) component is disposed above the first surface of the substrate. A buffer layer is disposed above the MEMS component, the buffer layer having a first Young's modulus. A mold compound is disposed above the buffer layer, the mold compound having a second Young's modulus higher than the first Young's modulus.

摘要翻译： 描述了用于集成微机电系统（MEMS）的应力缓冲层。 例如，半导体封装包括具有第一和第二表面的衬底，第二表面具有外部导电触点阵列。 微机电系统（MEMS）部件设置在基板的第一表面上方。 缓冲层设置在MEMS部件上方，缓冲层具有第一杨氏模量。 模具化合物设置在缓冲层上方，模塑料具有高于第一杨氏模量的第二杨氏模量。

公开(公告)号：US07433232B2

公开(公告)日：2008-10-07

申请号：US11431265

申请日：2006-05-10

申请人： Christian Geissler ,  Franz Schuler ,  Danny Pak-Chum Shum

发明人： Christian Geissler ,  Franz Schuler ,  Danny Pak-Chum Shum

IPC分类号： G11C16/04

CPC分类号： G11C16/0416

摘要： An integrated memory transistor and a memory unit including a plurality of integrated memory transistors is disclosed. Generally, the integrated memory transistor includes an electron source, a channel region, a control region, a charge storage region, a source-side pocket doping region, and a drain-side pocket doping region. The electron source is operable to transport electrons to the channel region when the integrated memory transistor operates in a read mode. Further, the electron source includes a drain terminal region and a source terminal region. The channel region is arranged between the drain terminal region and source terminal region. The charge storage region is arranged between the control region and the channel region. The source-side doping region is arranged nearer to the source terminal region than to the drain terminal region. The drain-side pocket doping region is arranged asymmetrical to the source-side pocket doping region.

摘要翻译： 公开了一种集成存储晶体管和包括多个集成存储晶体管的存储单元。 通常，集成存储晶体管包括电子源，沟道区，控制区，电荷存储区，源极侧掺杂区和漏极侧杂质掺杂区。 当集成存储晶体管以读取模式工作时，电子源可操作以将电子传输到沟道区域。 此外，电子源包括漏极端子区域和源极端子区域。 沟道区域设置在漏极端子区域和源极端子区域之间。 电荷存储区域设置在控制区域和沟道区域之间。 源极侧掺杂区域比漏极端子区域更靠近源极端子区域。 漏极侧杂质掺杂区域与源极侧掺杂区域不对称地布置。