公开(公告)号：US09484417B1

公开(公告)日：2016-11-01

申请号：US14805907

申请日：2015-07-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Manfred Eller

IPC: H01L29/167 ,  H01L29/161 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/66628 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1218 ,  H01L29/165 ,  H01L29/78603 ,  H01L29/78654 ,  H01L29/78684

Abstract: Methods of forming doped transition regions of transistor structures are provided herein. The methods include, for instance: providing a first semiconductor material including a dopant over a source/drain region of the transistor structure; providing a second semiconductor material including the dopant over the first semiconductor material, where the second semiconductor material is different from the first semiconductor material; and, where providing the second semiconductor material is performed at a temperature sufficient to diffuse the dopant from the first semiconductor material through the source/drain region into a portion of a channel region of the transistor structure. The portion of the channel region into which the dopant from the first semiconductor material diffuses forms the doped transition region.

Abstract translation: 本文提供了形成晶体管结构的掺杂过渡区的方法。 所述方法包括例如：在晶体管结构的源极/漏极区域上提供包括掺杂剂的第一半导体材料; 在所述第一半导体材料上提供包括所述掺杂剂的第二半导体材料，其中所述第二半导体材料不同于所述第一半导体材料; 并且其中提供第二半导体材料的温度足以将掺杂剂从第一半导体材料通过源/漏区扩散到晶体管结构的沟道区的一部分中。 来自第一半导体材料的掺杂剂扩散的沟道区的部分形成掺杂的过渡区。

公开(公告)号：US09455198B1

公开(公告)日：2016-09-27

申请号：US14676034

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  HongLiang Shen ,  Zhenyu Hu ,  Lun Zhao ,  Richard J. Carter ,  Xusheng Wu

IPC: H01L21/8234 ,  H01L21/308

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/66

Abstract: One illustrative method disclosed herein includes, among other things, removing at least one, but not all, of a plurality of first features in a first patterned mask layer so as to define a modified first patterned masking layer, wherein removed first feature(s) correspond to a location where a final isolation structure will be formed, performing an etching process though the modified first patterned masking layer to form an initial isolation trench in the substrate, and performing another etching process through the modified first patterned mask layer to thereby define a plurality of fin-formation trenches in the substrate and to extend a depth of the initial isolation trench so as to define a final isolation trench for the final isolation structure.

Abstract translation: 本文公开的一种说明性方法包括除去第一图案化掩模层中的多个第一特征中的至少一个但不是全部的，以便限定经修改的第一图案化掩模层，其中去除的第一特征 对应于将形成最终隔离结构的位置，通过经修改的第一图案化掩模层执行蚀刻工艺，以在衬底中形成初始隔离沟槽，以及通过修改的第一图案化掩模层执行另一蚀刻工艺，由此限定 在衬底中的多个翅片形成沟槽并且延伸初始隔离沟槽的深度，以便限定用于最终隔离结构的最终隔离沟槽。

公开(公告)号：US09343371B1

公开(公告)日：2016-05-17

申请号：US14725552

申请日：2015-05-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Jin Ping Liu

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/0924 ,  H01L21/2254 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823892 ,  H01L21/845 ,  H01L27/0922 ,  H01L29/0607 ,  H01L29/0649 ,  H01L29/167 ,  H01L29/66803

Abstract: Methods are provided for fabricating fin structures. The methods include: fabricating at least one fin structure, the at least one fin structure having a doped middle portion separating an upper portion from a lower portion, and the fabricating comprising: providing an isolation layer in contact with the lower portion of the at least one fin structure; forming a doping layer above the isolation layer and in contact with the at least one fin structure; and annealing the doping layer to diffuse dopants therefrom into the at least one fin structure to form the doped middle portion thereof, wherein the isolation layer inhibits diffusion of dopants from the doping layer into the lower portion of the at least one fin structure.

Abstract translation: 提供了用于制造翅片结构的方法。 所述方法包括：制造至少一个翅片结构，所述至少一个翅片结构具有将上部与下部分隔开的掺杂中间部分，并且所述制造包括：提供与所述至少下部的下部接触的隔离层 一个鳍结构; 在所述隔离层上方形成掺杂层并与所述至少一个翅片结构接触; 以及退火所述掺杂层以将掺杂剂从其中扩散到所述至少一个鳍结构中以形成其掺杂的中间部分，其中所述隔离层抑制掺杂剂从所述掺杂层扩散到所述至少一个鳍结构的下部。

公开(公告)号：US09299608B2

公开(公告)日：2016-03-29

申请号：US14281454

申请日：2014-05-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Changyong Xiao ,  Min-hwa Chi

IPC: H01L21/28 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/28518 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/485 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor, planar or non-planar (e.g., FinFET), includes T-shaped contacts to the source, drain and gate. The top portion of the T-shaped contact is wider than the bottom portion, the bottom portion complying with design rule limits. A conductor-material filled trench through a multi-layer etching stack above the transistor provides the top portions of the T-shaped contacts. Tapered spacers along inner sidewalls of the top contact portion prior to filling allow for etching a narrower bottom trench down to the gate, and to the source/drain for silicidation prior to filling.

Abstract translation: 晶体管，平面或非平面（例如，FinFET）包括到源极，漏极和栅极的T形接触。 T形接触件的顶部比底部宽，底部符合设计规则限制。 通过晶体管上方的多层蚀刻堆叠的导体材料填充沟槽提供了T形触头的顶部。 在填充之前，顶部接触部分的内侧壁上的锥形间隔物允许在填充之前将较窄的底部沟槽蚀刻到栅极和源极/漏极以进行硅化。

公开(公告)号：US20200020770A1

公开(公告)日：2020-01-16

申请号：US16033812

申请日：2018-07-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Hsien-Ching Lo ,  Xusheng Wu ,  Hui Zang ,  Zhenyu Hu ,  George R. Mulfinger

IPC: H01L29/08 ,  H01L29/66 ,  H01L21/8234

Abstract: Structures for field-effect transistors and methods for forming field-effect transistors. A sidewall spacer is arranged adjacent to a sidewall of a gate structure. The sidewall spacer includes a first section and a second section arranged over the first section. The first section of the sidewall spacer is composed of a first dielectric material, and the second section of the sidewall spacer is composed of a second dielectric material different from the first dielectric material. A source/drain region includes a first section arranged adjacent to the first section of the sidewall spacer and a second section arranged adjacent to the second section of the sidewall spacer. The second section of the source/drain region is spaced by a gap from the second section of the sidewall spacer.

公开(公告)号：US10522679B2

公开(公告)日：2019-12-31

申请号：US15797380

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ashish Kumar Jha ,  Hong Yu ,  Xinyuan Dou ,  Xusheng Wu ,  Dongil Choi ,  Edmund K. Banghart ,  Md Khaled Hassan

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/311

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to selective shallow trench isolation (STI) fill material for stress engineering in semiconductor structures and methods of manufacture. The structure includes a single diffusion break (SDB) region having at least one shallow trench isolation (STI) region with a stress fill material within a recess of the at least one STI region. The stress fill material imparts a stress on a gate structure adjacent to the at least one STI region.

公开(公告)号：US10388562B2

公开(公告)日：2019-08-20

申请号：US15678229

申请日：2017-08-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou Huang ,  Daniel Jaeger ,  Xusheng Wu ,  Jinsheng Gao

IPC: H01L21/336 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/02

Abstract: A composite etch stop layer includes an oxide layer formed over a sacrificial gate structure and a nitride layer formed over the oxide layer. The oxide layer is disposed over only lower portions of the sacrificial gate structure while the nitride layer envelops the oxide layer and is disposed directly over a top surface of the sacrificial gate structure. Sensitivity of the nitride layer to oxidation, such as during the formation of an interlayer dielectric over the composite etch stop layer, is decreased by eliminating the oxide layer from upper portions of the sacrificial gate layer.

公开(公告)号：US10347531B2

公开(公告)日：2019-07-09

申请号：US15438828

申请日：2017-02-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sipeng Gu ,  Xusheng Wu ,  Xinyuan Dou ,  Xiaobo Chen ,  Guoliang Zhu ,  Wenhe Lin ,  Jeffrey Chee

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532

Abstract: Disclosed are a method of forming an integrated circuit (IC) structure with robust metal plugs and the resulting IC structure. In the method, openings are formed in an interlayer dielectric layer to expose semiconductor device surfaces. The openings are lined with a two-layer liner, which includes conformal metal and barrier layers, and subsequently filled with a metal layer. However, instead of waiting until after the liner is formed to perform a silicidation anneal, as is conventionally done, the silicidation anneal is performed between deposition of the two liner layers. This is particularly useful because, as determined by the inventors, performing the silicidation anneal prior to depositing the conformal barrier layer prevents the formation of microcracks in the conformal barrier layer. Prevention of such microcracks, in turn, prevents any metal from the metal layer from protruding into the area between the two liner layers and/or completely through the liner.

公开(公告)号：US10217846B1

公开(公告)日：2019-02-26

申请号：US15873156

申请日：2018-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Steven Bentley ,  Min Gyu Sung ,  Chanro Park ,  Steven Soss ,  Hui Zang ,  Xusheng Wu ,  Yi Qi ,  Ajey P. Jacob ,  Murat K. Akarvardar ,  Siva P. Adusumilli ,  Jiehui Shu ,  Haigou Huang ,  John H. Zhang

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/336 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  H01L29/165 ,  H01L29/16 ,  H01L29/78

Abstract: Disclosed are a method of forming vertical field effect transistor(s) and the resulting structure. In the method, five semiconductor layers are formed in a stack by epitaxial deposition. The first and fifth layers are one semiconductor material, the second and fourth layers are another and the third layer is yet another. The stack is patterned into fin(s). Vertical surfaces of the second and fourth layers of the fin(s) are etched to form upper and lower spacer cavities and these cavities are filled with upper and lower spacers. Vertical surfaces of the third layer of the fin(s) are etched to form a gate cavity and this cavity is filled with a gate. Since epitaxial deposition is used to form the semiconductor layers, the thicknesses of these layers and thereby the heights of the spacer cavities and gate cavity and the corresponding lengths of the spacers and gate can be precisely controlled.

公开(公告)号：US10211317B1

公开(公告)日：2019-02-19

申请号：US15869349

申请日：2018-01-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Xusheng Wu ,  Jianwei Peng ,  Sipeng Gu ,  Hsien-Ching Lo

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L21/762 ,  H01L21/311 ,  H01L21/02 ,  H01L29/78 ,  H01L21/3105

Abstract: Methods of forming a structure for a vertical-transport field-effect transistor. A semiconductor fin is formed over a sacrificial layer. A support structure is connected with the semiconductor fin. After forming the support structure, the sacrificial layer is removed to form a cavity extending beneath the semiconductor fin. A semiconductor material is epitaxially grown in the cavity to form a source/drain region of the vertical-transport field-effect transistor.