公开(公告)号：US20160190302A1

公开(公告)日：2016-06-30

申请号：US14585742

申请日：2014-12-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Dominic J. Schepis

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/06 ,  H01L29/167 ,  H01L21/84 ,  H01L21/02 ,  H01L21/322 ,  H01L21/324 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/7624 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device where: (i) the fins are formed over a porous semiconductor material layer (for example, a silicon layer); and (ii) the porous semiconductor layer is then oxidized to form an insulator layer (for example, a SiO2 buried oxide layer). The pores in the porous semiconductor layer facilitate reliable oxidation of the insulator layer by allowing penetration of gaseous oxygen (O2) throughout the layer as it is oxidized to form the insulator layer. In some of these embodiments, a thin non-porous semiconductor layer is located over the porous semiconductor layer (prior to its oxidation) to allow strained epitaxial growth of material to be used in making source regions and drain regions of the finished semiconductor device (for example, a FINFET).

Abstract translation: 一种制造半导体器件的方法，其中：（i）所述散热片形成在多孔半导体材料层（例如，硅层）上; 和（ii）然后氧化多孔半导体层以形成绝缘体层（例如，SiO 2掩埋氧化物层）。 多孔半导体层中的孔促进了绝缘体层的可靠氧化，允许气态氧（O 2）在整个层中被氧化以形成绝缘体层。 在这些实施例的一些中，薄的无孔半导体层位于多孔半导体层之上（在其氧化之前），以允许材料的应变外延生长用于制造成品半导体器件的源极区域和漏极区域（用于 例如，FINFET）。

公开(公告)号：US20160181095A1

公开(公告)日：2016-06-23

申请号：US14574533

申请日：2014-12-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kanggou Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L21/02 ,  H01L29/161 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/02532 ,  H01L21/02422 ,  H01L21/0245 ,  H01L21/02587 ,  H01L21/02612 ,  H01L21/02664 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/161 ,  H01L29/66795

Abstract: Embodiments of the invention include a method for fabricating a SiGe fin and the resulting structure. A SOI substrate is provided, including at least a silicon layer on top of a BOX. At least one fin upon a thin layer of silicon and a hard mask layer over the at least one fin is formed using the silicon layer on top of the BOX. A SiGe layer is epitaxially grown from exposed portions of the fin and the thin layer of silicon. Spacers are formed on sidewalls of the hard mask. Regions of the SiGe layer and the thin layer of silicon not protected by the spacers are etched, such that portions of the BOX are exposed. A condensation process converts the fin to SiGe and to convert the SiGe layer to oxide. The hard mask, the spacers, and the oxide layer are removed.

Abstract translation: 本发明的实施例包括制造SiGe鳍片的方法和所得到的结构。 提供SOI衬底，其至少包括在BOX顶部的硅层。 使用BOX顶部的硅层，在至少一个散热片上的薄层硅层和硬掩模层上形成至少一个鳍片。 SiGe层从翅片和薄层硅的暴露部分外延生长。 垫片形成在硬掩模的侧壁上。 SiGe层的区域和未被间隔物保护的硅的薄层被蚀刻，使得BOX的部分被暴露。 冷凝过程将翅片转换成SiGe并将SiGe层转化为氧化物。 去除硬掩模，间隔物和氧化物层。

公开(公告)号：US20160163879A1

公开(公告)日：2016-06-09

申请号：US15009906

申请日：2016-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L27/12

CPC classification number: H01L29/78648 ,  H01L21/28008 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42364

Abstract: A semiconductor device is disclosed. The semiconductor device can include a first dielectric layer disposed on a substrate; a set of bias lines disposed on the first dielectric layer; a second dielectric layer disposed on the first dielectric layer and between the set of bias lines, wherein a thickness of the second dielectric layer is less than a thickness of the first dielectric layer; a patterned semiconductor layer disposed on portions of the second dielectric layer; and a set of devices disposed on the patterned semiconductor layer above the set of bias lines.

Abstract translation: 公开了一种半导体器件。 半导体器件可以包括设置在衬底上的第一介电层; 设置在所述第一电介质层上的一组偏置线; 第二电介质层，设置在所述第一电介质层上和所述一组偏置线之间，其中所述第二电介质层的厚度小于所述第一介电层的厚度; 设置在所述第二电介质层的部分上的图案化半导体层; 以及设置在所述偏置线组之上的图案化半导体层上的一组器件。

公开(公告)号：US09349835B2

公开(公告)日：2016-05-24

申请号：US14027720

申请日：2013-09-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Charan Veera Venkata Satya Surisetty

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/49 ,  H01L29/417 ,  H01L29/51

CPC classification number: H01L27/0886 ,  H01L21/76837 ,  H01L21/76897 ,  H01L21/823468 ,  H01L29/41766 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795

Abstract: A semiconductor device includes gates and a low-k spacer. The low-k spacer includes low-k spacer portions formed upon the gate sidewalls and a low-k spacer portion formed upon a top surface of an underlying substrate adjacent to the gates. When a structure has previously undergone a gate processing fabrication stage, the gates and at least a portion of the top surface of the substrate may be exposed thereby allowing the formation of the low-k spacer. This exposure may include removing any original gate spacers, removing an original liner formed upon the original spacers, and removing any original fill material formed upon the liner.

Abstract translation: 半导体器件包括栅极和低k间隔物。 低k间隔物包括形成在栅极侧壁上的低k隔离部分和形成在与栅极相邻的下面基底的顶表面上的低k隔离部分。 当结构先前已经进行了栅极处理制造阶段时，可以暴露栅极和衬底顶表面的至少一部分，从而允许形成低k间隔物。 该曝光可以包括去除任何原始的栅极间隔物，去除形成在原始间隔物上的原始衬垫，以及去除在衬垫上形成的任何原始填充材料。

公开(公告)号：US20160133727A1

公开(公告)日：2016-05-12

申请号：US14537832

申请日：2014-11-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Pouya Hashemi ,  Shogo Mochizuki ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor structure, such as a FinFET, etc., includes a bi-portioned junction. The bi-portioned junction includes a doped outer portion and a doped inner portion. The dopant concentration of the outer portion is less than the dopant concentration of the inner portion. An electrical connection is formed by diffusion of the dopants within outer portion into a channel region and diffusion of the dopants within the outer portion into the inner region. A low contact resistance is achieved by a contact electrically contacting the relatively higher doped inner portion while device shorting is limited by the relatively lower doped outer portion.

Abstract translation: 诸如FinFET等的半导体结构包括双分支结。 双分支结包括掺杂的外部部分和掺杂的内部部分。 外部部分的掺杂剂浓度小于内部部分的掺杂剂浓度。 通过将外部部分内的掺杂剂扩散到沟道区域中并且将外部部分内的掺杂剂扩散到内部区域中来形成电连接。 低接触电阻通过电接触相对较高的掺杂内部部分的接触来实现，同时器件短路由相对较低的掺杂外部部分限制。

公开(公告)号：US09330908B2

公开(公告)日：2016-05-03

申请号：US13925911

申请日：2013-06-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/02 ,  H01L21/8258 ,  H01L21/8238 ,  H01L27/088

CPC classification number: H01L21/02538 ,  H01L21/02373 ,  H01L21/02441 ,  H01L21/02447 ,  H01L21/02494 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/088

Abstract: A semiconductor structure includes a first semiconductor region. The first semiconductor region includes a first semiconductor layer composed of a group IV semiconductor material having a top surface and a back surface. The first semiconductor layer has an opening in the top surface to at least a depth greater than an aspect ratio trapping (ART) distance. The first semiconductor region also has a second semiconductor layer composed of a group III/V semiconductor compound deposited within the opening and on the top surface of the first semiconductor layer. The second semiconductor layer forms an ART region from the bottom of the opening to the ART distance.

Abstract translation: 半导体结构包括第一半导体区域。 第一半导体区域包括由具有顶表面和后表面的IV族半导体材料组成的第一半导体层。 第一半导体层在顶表面具有至少大于纵横比捕获（ART）距离的深度的开口。 第一半导体区域还具有由沉积在第一半导体层的开口内和顶表面上的III / V族半导体化合物构成的第二半导体层。 第二半导体层从开口的底部到ART距离形成ART区域。

公开(公告)号：US09324797B2

公开(公告)日：2016-04-26

申请号：US14751761

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L51/00 ,  H01L29/49 ,  H01L29/775 ,  H01L29/423 ,  H01L29/51 ,  H01L29/10 ,  H01L29/786 ,  H01L29/08

CPC classification number: H01L29/42392 ,  H01L21/8238 ,  H01L21/82385 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78696 ,  H01L51/0048

Abstract: A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench.

公开(公告)号：US09281198B2

公开(公告)日：2016-03-08

申请号：US13900808

申请日：2013-05-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan

IPC: H01L21/28 ,  H01L21/84 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L29/78648 ,  H01L21/28008 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42364

Abstract: A method of forming a semiconductor device is disclosed. The method includes forming a first dielectric layer on a substrate; forming a set of bias lines on the first dielectric layer; covering the set of bias lines with a second dielectric layer; forming a semiconductor layer on the second dielectric layer; and forming a set of devices on the semiconductor layer above the set of bias lines.

Abstract translation: 公开了一种形成半导体器件的方法。 该方法包括在基底上形成第一介电层; 在所述第一电介质层上形成一组偏置线; 用第二电介质层覆盖该组偏置线; 在所述第二电介质层上形成半导体层; 以及在所述偏置线组之上的半导体层上形成一组器件。

公开(公告)号：US09257531B2

公开(公告)日：2016-02-09

申请号：US14481178

申请日：2014-09-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Soon-Cheon Seo ,  Balasubramanian S. Haran ,  Alexander Reznicek

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L21/283 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/51

CPC classification number: H01L29/66636 ,  H01L21/0223 ,  H01L21/02636 ,  H01L21/28158 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7833

Abstract: A metallic top surface of a replacement gate structure is oxidized to convert a top portion of the replacement gate structure into a dielectric oxide. After removal of a planarization dielectric layer, selective epitaxy is performed to form a raised source region and a raised drain region that extends higher than the topmost surface of the replacement gate structure. A gate level dielectric layer including a first dielectric material is deposited and subsequently planarized employing the raised source and drain regions as stopping structures. A contact level dielectric layer including a second dielectric material is formed over the gate level dielectric layer, and contact via holes are formed employing an etch chemistry that etches the second dielectric material selective to the first dielectric material. Raised source and drain regions are recessed. Self-aligned contact structures can be formed by filling the contact via holes with a conductive material.

公开(公告)号：US08809920B2

公开(公告)日：2014-08-19

申请号：US13670674

申请日：2012-11-07

Applicant: International Business Machines Corporation ,  GlobalFoundries Inc.

Inventor： Ali Khakifirooz ,  Thomas N. Adam ,  Kangguo Cheng ,  Shom Ponoth ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L29/76

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.

Abstract translation: 在形成一次性栅极结构之前，介电金属化合物衬垫可沉积在半导体鳍片上。 介电金属复合衬里在一​​次性栅极结构和栅极间隔物的图案期间保护半导体鳍片。 在形成源极和漏极区域和替换栅极结构之前，可以去除电介质金属化合物衬垫。 或者，介电金属化合物衬垫可以沉积在半导体鳍片和栅极叠层上，并且可以在形成栅极间隔物之后被去除。 此外，可以在半导体鳍片和一次性栅极结构上沉积电介质金属化合物衬垫，并且可以在形成栅极间隔物和去除一次性栅极结构之后被去除。 在各实施例中，介电金属化合物衬垫可以在形成栅极间隔物期间保护半导体鳍片。