公开(公告)号：US20170104100A1

公开(公告)日：2017-04-13

申请号：US14879220

申请日：2015-10-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Emre Alptekin ,  Lars W. Liebmann ,  Injo Ok ,  Balasubramanian Pranatharthiharan ,  Ravikumar Ramachandran ,  Soon-Cheon Seo ,  Charan V.V.S. Surisetty ,  Mickey H. Yu

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L21/32139 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/66636 ,  H01L29/66795

Abstract: Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming a doped silicon layer over a substrate; forming a plurality of fin structures from the doped silicon layer; forming a plurality of gate structures over the plurality of fin structures, each of the plurality of gate structures separated from a neighboring gate structure by a first pitch; forming a mask over the plurality of gate structures, exposing at least one of the plurality of gate structures; removing the at least one of the plurality of gate structures, wherein two of the remaining gate structures after the removing are separated by a second pitch larger than the first pitch; and forming an epitaxial region over the substrate between the two of the remaining gate structures.

公开(公告)号：US09257531B2

公开(公告)日：2016-02-09

申请号：US14481178

申请日：2014-09-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Soon-Cheon Seo ,  Balasubramanian S. Haran ,  Alexander Reznicek

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L21/283 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/51

CPC classification number: H01L29/66636 ,  H01L21/0223 ,  H01L21/02636 ,  H01L21/28158 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7833

Abstract: A metallic top surface of a replacement gate structure is oxidized to convert a top portion of the replacement gate structure into a dielectric oxide. After removal of a planarization dielectric layer, selective epitaxy is performed to form a raised source region and a raised drain region that extends higher than the topmost surface of the replacement gate structure. A gate level dielectric layer including a first dielectric material is deposited and subsequently planarized employing the raised source and drain regions as stopping structures. A contact level dielectric layer including a second dielectric material is formed over the gate level dielectric layer, and contact via holes are formed employing an etch chemistry that etches the second dielectric material selective to the first dielectric material. Raised source and drain regions are recessed. Self-aligned contact structures can be formed by filling the contact via holes with a conductive material.

公开(公告)号：US09806078B1

公开(公告)日：2017-10-31

申请号：US15341240

申请日：2016-11-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Christopher Prindle ,  Tenko Yamashita ,  Balasubramanian Pranatharthiharan ,  Pietro Montanini ,  Soon-Cheon Seo

IPC: H01L21/8238 ,  H01L29/78 ,  H01L27/092 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L27/0924 ,  H01L21/31055 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7856

Abstract: FinFET spacer formation includes, for example, providing an intermediate semiconductor structure having a substrate having one or more fin having a first and a second plurality of gates disposed thereon, and a first plurality of spacers disposed on sides of the first and second plurality of gates, depositing a first liner on the structure, depositing a fill material at a level along inner portions of the first liner between the gates adjacent to the one or more fin, removing outer portions of the first spacers and the first liner away from the fill material, the remaining portions of the first spacers and the first liner defining a first thickness, and depositing a second liner having a second thickness over the gates and over the remaining portions of the first spacers and the first liner, and the fill material, and wherein the first thickness is greater than the second thickness.

公开(公告)号：US09653573B2

公开(公告)日：2017-05-16

申请号：US14827510

申请日：2015-08-17

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Linus Jang ,  Sivananda K. Kanakasabapathy ,  Sanjay C. Mehta ,  Soon-Cheon Seo ,  Raghavasimhan Sreenivasan

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/311

CPC classification number: H01L29/66545 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.

公开(公告)号：US20140329388A1

公开(公告)日：2014-11-06

申请号：US13874577

申请日：2013-05-01

Applicant: GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Linus Jang ,  Soon-Cheon Seo ,  Ryan O. Jung

IPC: H01L21/311

CPC classification number: H01L21/3085 ,  H01L21/0337 ,  H01L21/28141 ,  H01L21/283 ,  H01L21/3081 ,  H01L21/32139 ,  H01L21/82385 ,  H01L29/6656

Abstract: Disclosed herein are methods of patterning features that have differing widths. In one example, the method includes forming a layer of material above a semiconductor substrate, forming a masking layer above the layer of material, wherein the masking layer is comprised of a first plurality features positioned above a first region of the semiconductor substrate and a second plurality of features positioned above a second region of the semiconductor substrate, wherein the first and second plurality of features have the same pitch spacing and wherein the first and second plurality of features have different widths, and performing at least one etching process on the layer of material through the masking layer.

Abstract translation: 本文公开了具有不同宽度的图案特征的方法。 在一个示例中，该方法包括在半导体衬底之上形成材料层，在材料层之上形成掩模层，其中掩模层由位于半导体衬底的第一区域上方的第一多个特征构成，第二 多个特征位于所述半导体衬底的第二区域之上，其中所述第一和第二多个特征具有相同的间距间距，并且其中所述第一和第二多个特征具有不同的宽度，并且对所述第一和第二多个特征层进行至少一个蚀刻处理 材料通过掩模层。

公开(公告)号：US20160064236A1

公开(公告)日：2016-03-03

申请号：US14935767

申请日：2015-11-09

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Linus Jang ,  Soon-Cheon Seo ,  Ryan O. Jung

IPC: H01L21/308 ,  H01L29/66 ,  H01L21/283

CPC classification number: H01L21/3085 ,  H01L21/0337 ,  H01L21/28141 ,  H01L21/283 ,  H01L21/3081 ,  H01L21/32139 ,  H01L21/82385 ,  H01L29/6656

Abstract: A method includes forming a layer of material above a semiconductor substrate and performing a first sidewall image transfer process to form a first plurality of spacers and a second plurality of spacers above the layer of material, wherein the first and second pluralities of spacers are positioned above respective first and second regions of the semiconductor substrate and have a same initial width and a same pitch spacing. A masking layer is formed above the layer of material so as to cover the first plurality of spacers and expose the second plurality of spacers, and a first etching process is performed through the masking layer on the exposed second plurality of spacers so as to form a plurality of reduced-width spacers having a width that is less than the initial width, wherein the first plurality of spacers and the plurality of reduced-width spacers define an etch mask.

Abstract translation: 一种方法包括在半导体衬底上形成材料层并执行第一侧壁图像转移工艺以在材料层之上形成第一多个间隔物和第二多个间隔物，其中第一和第二多个间隔物位于 相应的半导体衬底的第一和第二区域，并且具有相同的初始宽度和相同的间距间距。 在材料层的上方形成掩模层，以便覆盖第一多个间隔物并露出第二多个间隔物，并且通过暴露的第二多个间隔物上的掩模层进行第一蚀刻工艺，从而形成 多个宽度窄于所述初始宽度的宽度窄的间隔物，其中所述第一多个间隔物和所述多个减小宽度的间隔物限定蚀刻掩模。

公开(公告)号：US09214360B2

公开(公告)日：2015-12-15

申请号：US13874577

申请日：2013-05-01

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Linus Jang ,  Soon-Cheon Seo ,  Ryan O. Jung

IPC: H01L21/311 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/28 ,  H01L21/8238

CPC classification number: H01L21/3085 ,  H01L21/0337 ,  H01L21/28141 ,  H01L21/283 ,  H01L21/3081 ,  H01L21/32139 ,  H01L21/82385 ,  H01L29/6656

Abstract: Disclosed herein are methods of patterning features that have differing widths. In one example, the method includes forming a layer of material above a semiconductor substrate, forming a masking layer above the layer of material, wherein the masking layer is comprised of a first plurality features positioned above a first region of the semiconductor substrate and a second plurality of features positioned above a second region of the semiconductor substrate, wherein the first and second plurality of features have the same pitch spacing and wherein the first and second plurality of features have different widths, and performing at least one etching process on the layer of material through the masking layer.

Abstract translation: 本文公开了具有不同宽度的图案特征的方法。 在一个示例中，该方法包括在半导体衬底之上形成材料层，在材料层之上形成掩模层，其中掩模层由位于半导体衬底的第一区域上方的第一多个特征构成，第二 多个特征位于所述半导体衬底的第二区域之上，其中所述第一和第二多个特征具有相同的间距间距，并且其中所述第一和第二多个特征具有不同的宽度，并且对所述第一和第二多个特征层进行至少一个蚀刻处理 材料通过掩模层。

公开(公告)号：US09685384B1

公开(公告)日：2017-06-20

申请号：US15210012

申请日：2016-07-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Christopher Prindle ,  Soon-Cheon Seo ,  Balasubramanian Pranatharthiharan ,  Pietro Montanini ,  Shogo Mochizuki

IPC: H01L21/70 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L21/823821 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/6656 ,  H01L29/66795

Abstract: Devices and methods of fabricating integrated circuit devices for forming epi for aggressive gate pitch are provided. One method includes: obtaining an intermediate semiconductor device having a substrate, a fin structure, a plurality of stacks; etching the spacer between the plurality of stacks; growing, epitaxially, undoped silicon on a top surface of the fin structure between the plurality of stacks; depositing a liner over the undoped silicon and the plurality of stacks; etching to remove the liner and narrow the spacers, wherein the etching forms a wider portion of the spacer at the base of the stacks; etching between the plurality of stacks to remove the undoped silicon and form recesses in the fin structure; and growing, epitaxially, doped silicon between the plurality of stacks and in the fin structure. Also disclosed is an intermediate device formed by the method.

公开(公告)号：US09466505B2

公开(公告)日：2016-10-11

申请号：US14935767

申请日：2015-11-09

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Linus Jang ,  Soon-Cheon Seo ,  Ryan O. Jung

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/283 ,  H01L29/66

CPC classification number: H01L21/3085 ,  H01L21/0337 ,  H01L21/28141 ,  H01L21/283 ,  H01L21/3081 ,  H01L21/32139 ,  H01L21/82385 ,  H01L29/6656

Abstract: A method includes forming a layer of material above a semiconductor substrate and performing a first sidewall image transfer process to form a first plurality of spacers and a second plurality of spacers above the layer of material, wherein the first and second pluralities of spacers are positioned above respective first and second regions of the semiconductor substrate and have a same initial width and a same pitch spacing. A masking layer is formed above the layer of material so as to cover the first plurality of spacers and expose the second plurality of spacers, and a first etching process is performed through the masking layer on the exposed second plurality of spacers so as to form a plurality of reduced-width spacers having a width that is less than the initial width, wherein the first plurality of spacers and the plurality of reduced-width spacers define an etch mask.

Abstract translation: 一种方法包括在半导体衬底上形成材料层并执行第一侧壁图像转移工艺以在材料层之上形成第一多个间隔物和第二多个间隔物，其中第一和第二多个间隔物位于 相应的半导体衬底的第一和第二区域，并且具有相同的初始宽度和相同的间距间距。 在材料层的上方形成掩模层，以便覆盖第一多个间隔物并露出第二多个间隔物，并且通过暴露的第二多个间隔物上的掩模层进行第一蚀刻工艺，从而形成 多个宽度窄于所述初始宽度的宽度窄的间隔物，其中所述第一多个间隔物和所述多个减小宽度的间隔物限定蚀刻掩模。

公开(公告)号：US20160172467A1

公开(公告)日：2016-06-16

申请号：US15062465

申请日：2016-03-07

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Linus Jang ,  Sivananda K. Kanakasabapathy ,  Sanjay C. Mehta ,  Soon-Cheon Seo ,  Raghavasimhan Sreenivasan

IPC: H01L29/66 ,  H01L21/3065 ,  H01L21/8234 ,  H01L21/283

CPC classification number: H01L29/66545 ,  H01L21/02164 ,  H01L21/2018 ,  H01L21/28238 ,  H01L21/3065 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7855 ,  H01L2029/7858

Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.