公开(公告)号：US09449887B2

公开(公告)日：2016-09-20

申请号：US14563009

申请日：2014-12-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Takashi Ando ,  Balaji Kannan ,  Vijay Narayanan

IPC: H01L21/8238 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/823828 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/66871

Abstract: A method of forming a transistor device includes forming an interfacial layer and a dielectric layer over a substrate; and forming a workfunction metal layer over the dielectric layer, the workfunction metal layer comprising a titanium-aluminum-carbon-oxygen (TiAlCO) layer.

Abstract translation: 形成晶体管器件的方法包括在衬底上形成界面层和电介质层; 以及在所述电介质层上形成功函数金属层，所述功函数金属层包含钛 - 铝 - 碳 - 氧（TiAlCO）层。

公开(公告)号：US20160104707A1

公开(公告)日：2016-04-14

申请号：US14513725

申请日：2014-10-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Balaji Kannan ,  Unoh Kwon ,  Rekha Rajaram

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/49 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L21/225

CPC classification number: H01L27/0922 ,  H01L21/02192 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/2255 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/517

Abstract: Embodiments of the present invention provide CMOS structures and methods of gate formation that combine a keep-cap scheme in which a protective layer is maintained on a PFET during a replacement metal gate process that utilizes an NFET-first process flow. Selective nitridation is used to provide nitrogen to the NFET while the PFET is protected from nitrogen by the keep-cap. Additional dopants are provided to the NFET using a gate stack dopant material (GSDM) layer.

Abstract translation: 本发明的实施例提供了CMOS结构和栅极形成方法，其组合了在利用NFET第一工艺流程的替换金属栅极工艺期间在PFET上保持保护层的保持帽方案。 选择性氮化用于向NFET提供氮气，同时PFET通过保护盖被氮保护。 使用栅极堆叠掺杂剂材料（GSDM）层向NFET提供附加的掺杂剂。

公开(公告)号：US20160086860A1

公开(公告)日：2016-03-24

申请号：US14495170

申请日：2014-09-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Balaji Kannan ,  Rekha Rajaram ,  Unoh Kwon

IPC: H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78

Abstract: A method of fabricating advanced multi-threshold field effect transistors using a replacement metal gate process. A first method includes thinning layers composed of multilayer film stacks and incorporating a portion of the remaining thinned film in some transistors. A second method includes patterning dopant materials for a high-k dielectric by using thinning layers composed of multilayer thin film stacks, or in other embodiments, by a single thinning layer.

Abstract translation: 使用替代金属栅极工艺制造先进的多阈值场效应晶体管的方法。 第一种方法包括由多层膜叠层组成的薄化层，并将一部分剩余的薄膜结合在一些晶体管中。 第二种方法包括通过使用由多层薄膜叠层组成的薄化层，或在其它实施例中，通过单个变薄层来图案化用于高k电介质的掺杂剂材料。

公开(公告)号：US10741668B2

公开(公告)日：2020-08-11

申请号：US15654234

申请日：2017-07-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bala Haran ,  Ruilong Xie ,  Balaji Kannan ,  Katsunori Onishi ,  Vimal K. Kamineni

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/161 ,  H01L21/285 ,  H01L29/78 ,  H01L27/092

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to replacement metal gate structures and methods of manufacture. The structure includes at least one short channel device including a dielectric material, a workfunction metal, and a capping material, and a long channel device comprising the dielectric material, the workfunction metal and fluorine free gate conductor material.

公开(公告)号：US10446550B2

公开(公告)日：2019-10-15

申请号：US15783549

申请日：2017-10-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Balaji Kannan ,  Ayse M. Ozbek ,  Tao Chu ,  Bala Haran ,  Vishal Chhabra ,  Katsunori Onishi ,  Guowei Xu

IPC: H01L27/092 ,  H01L29/06 ,  H01L27/02 ,  H01L21/311 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/027 ,  H01L21/8238 ,  H01L29/51 ,  H01L27/11

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cut inside a replacement metal gate trench to mitigate n-p proximity effects and methods of manufacture. The structure described herein includes: a first device; a second device, adjacent to the first device; a dielectric material, of the first device and the second device, including a cut within a trench between the first device and the second device; and a common gate electrode shared with the first device and the second device, the common gate electrode provided over the dielectric material and contacting underlying material within the cut.

公开(公告)号：US10332747B1

公开(公告)日：2019-06-25

申请号：US15878519

申请日：2018-01-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Koji Watanabe ,  Meng Zhu ,  Brian A. Cohen ,  Matthew T. Whitman ,  Balaji Kannan

IPC: H01L21/8234 ,  H01L21/285 ,  H01L29/49 ,  H01L29/51 ,  C23C16/34 ,  C23C16/455 ,  C23C16/04 ,  H01L21/28

Abstract: In an exemplary method, a dielectric layer is deposited on a substrate. A masking layer is formed over a first region and a second region of the dielectric layer. The masking layer is made of an oxide of lanthanum. The masking layer is removed from the second region of the dielectric layer. A work function layer is formed directly on only the second region of the dielectric layer. The work function layer is made of titanium nitride that is formed by using a combination of titanium tetrachloride and ammonia (TiCl4/NH3).

公开(公告)号：US20190096679A1

公开(公告)日：2019-03-28

申请号：US15712996

申请日：2017-09-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Balaji Kannan ,  Bala Haran ,  Vimal K. Kamineni ,  Sungkee Han ,  Neal Makela ,  Suraj K. Patil ,  Pei Liu ,  Chih-Chiang Chang ,  Katsunori Onishi ,  Keith Kwong Hon Wong ,  Ruilong Xie ,  Chanro Park ,  Min Gyu Sung

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

Abstract: Structures for a field-effect transistor and methods for forming a structure for a field-effect transistor. A gate cavity is formed in a dielectric layer that includes a bottom surface and a plurality sidewalls that extend to the bottom surface. A gate dielectric layer is formed at the sidewalls and the bottom surface of the gate cavity. A work function metal layer is deposited on the gate dielectric layer at the sidewalls and the bottom surface of the gate cavity. A fill metal layer is deposited inside the gate cavity after the work function metal layer is deposited. The fill metal layer is formed in direct contact with the work function metal layer.

公开(公告)号：US10170373B2

公开(公告)日：2019-01-01

申请号：US14495170

申请日：2014-09-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Balaji Kannan ,  Rekha Rajaram ,  Unoh Kwon

IPC: H01L21/8238

Abstract: A method of fabricating advanced multi-threshold field effect transistors using a replacement metal gate process. A first method includes thinning layers composed of multilayer film stacks and incorporating a portion of the remaining thinned film in some transistors. A second method includes patterning dopant materials for a high-k dielectric by using thinning layers composed of multilayer thin film stacks, or in other embodiments, by a single thinning layer.

公开(公告)号：US09691662B2

公开(公告)日：2017-06-27

申请号：US15338894

申请日：2016-10-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Takashi Ando ,  Min Dai ,  Balaji Kannan ,  Siddarth A. Krishnan ,  Unoh Kwon

IPC: H01L21/8234 ,  H01L29/49 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/324 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L21/823412 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/785

Abstract: Selective deposition of a silicon-germanium surface layer on semiconductor surfaces can be employed to provide two types of channel regions for field effect transistors. Anneal of an adjustment oxide material on a stack of a silicon-based gate dielectric and a high dielectric constant (high-k) gate dielectric can be employed to form an interfacial adjustment oxide layer contacting a subset of channel regions. Oxygen deficiency can be induced in portions of the high-k dielectric layer overlying the interfacial adjustment oxide layer by deposition of a first work function metallic material layer and a capping layer and a subsequent anneal. Oxygen deficiency can be selectively removed by physically exposing portions of the high-k dielectric layer. A second work function metallic material layer and a gate conductor layer can be deposited and planarized to form gate electrodes that provide multiple effective work functions.

公开(公告)号：US20160351453A1

公开(公告)日：2016-12-01

申请号：US14721402

申请日：2015-05-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Takashi Ando ,  Aritra Dasgupta ,  Balaji Kannan ,  Unoh Kwon

IPC: H01L21/8238 ,  H01L29/49 ,  H01L29/423 ,  H01L21/324 ,  H01L27/092

CPC classification number: H01L21/823857 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/324 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/105 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: Embodiments of the present invention provide a process that maintains a “keep cap” metal nitride layer on PFET devices within a CMOS structure. The keep cap metal nitride layer is in place while an N-type work function metal is formed on the NFET devices within the CMOS structure. A sacrificial rare earth oxide layer, such as a lanthanum oxide layer is used to facilitate removal of the n-type work function metal selective to the keep cap metal nitride layer.

Abstract translation: 本发明的实施例提供了在CMOS结构内在PFET器件上保持“保持帽”金属氮化物层的工艺。 在CMOS结构内的NFET器件上形成N型功函数金属时，保持帽金属氮化物层就位。 使用诸如氧化镧层的牺牲稀土氧化物层来去除对保持帽金属氮化物层有选择性的n型功函数金属。