公开(公告)号：US09608110B2

公开(公告)日：2017-03-28

申请号：US14812245

申请日：2015-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Carsten Grass

IPC: H01L21/00 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L29/51 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/11592

CPC classification number: H01L29/78391 ,  H01L21/28185 ,  H01L21/28291 ,  H01L21/823462 ,  H01L21/823857 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1159 ,  H01L27/11592 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545

Abstract: The present disclosure provides methods of forming a semiconductor circuit element and a semiconductor circuit element, wherein the semiconductor circuit element includes a first semiconductor device with a first gate structure disposed over a first active region of a semiconductor substrate and a second semiconductor device with a second gate structure disposed over a second active region of the semiconductor substrate, the first gate structure comprising a ferroelectric material buried into the first active region before a gate electrode material is formed on the ferroelectric material and the second gate structure comprising a high-k material different from the ferroelectric material.

公开(公告)号：US09583640B1

公开(公告)日：2017-02-28

申请号：US14982028

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Sven Beyer ,  Carsten Grass ,  Tom Herrmann

IPC: H01L29/788 ,  H01L29/66 ,  H01L29/423 ,  H01L27/115

CPC classification number: H01L29/7887 ,  H01L27/11531 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/665 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method comprises providing a semiconductor structure including a nonvolatile memory cell element comprising a floating gate, a select gate and an erase gate formed over a semiconductor material, the select gate and the erase gate being arranged at opposite sides of the floating gate, forming a control gate insulation material layer over the semiconductor structure, forming a control gate material layer over the control gate insulation material layer, performing a first patterning process that forms a control gate over the floating gate and comprises a first etch process that selectively removes a material of the control gate material layer relative to a material of the control gate insulation material layer, and performing a second patterning process that patterns the control gate insulation material layer, the patterned control gate insulation material layer covering portions of the semiconductor structure that are not covered by the control gate.

Abstract translation: 一种方法包括提供包括非易失性存储单元元件的半导体结构，所述非易失性存储单元元件包括在半导体材料上形成的浮置栅极，选择栅极和擦除栅极，所述选择栅极和擦除栅极被布置在所述浮置栅极的相对侧， 控制栅极绝缘材料层，在所述控制栅极绝缘材料层上方形成控制栅极材料层，执行在所述浮动栅极上形成控制栅极的第一图案化工艺，并且包括第一蚀刻工艺，所述第一蚀刻工艺选择性地去除 所述控制栅极材料层相对于所述控制栅极绝缘材料层的材料，并且执行对所述控制栅极绝缘材料层进行图案化的第二图案化工艺，所述图案化的控制栅极绝缘材料层覆盖所述半导体结构的不被 控制门。

公开(公告)号：US20160049302A1

公开(公告)日：2016-02-18

申请号：US14458718

申请日：2014-08-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Carsten Grass ,  Peter Baars

IPC: H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/51

CPC classification number: H01L21/28194 ,  H01L21/28185 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545

Abstract: The present disclosure provides a method of forming a semiconductor circuit element and a semiconductor circuit element, wherein the semiconductor circuit element is formed on the basis of a replacement gate process replacing a dummy gate structure of a semiconductor device of the semiconductor circuit element by a gate oxide structure and a gate electrode material, wherein the gate oxide structure comprises a high-k material that is in the ferroelectric phase. In some illustrative embodiments herein, a semiconductor device is provided, the semiconductor device having a gate structure disposed over an active region of a semiconductor substrate. Herein, the gate structure comprises a spacer structure and a dummy gate structure which is replaced by a gate oxide structure and a gate electrode material, wherein the gate oxide structure comprises a ferroelectric high-k material.

Abstract translation: 本公开提供了一种形成半导体电路元件和半导体电路元件的方法，其中，基于替换栅极工艺形成半导体电路元件，替代栅极工艺通过栅极替代半导体电路元件的半导体器件的伪栅极结构 氧化物结构和栅电极材料，其中栅极氧化物结构包括处于铁电相中的高k材料。 在本文的一些说明性实施例中，提供半导体器件，该半导体器件具有设置在半导体衬底的有源区上方的栅极结构。 这里，栅极结构包括由栅极氧化物结构和栅电极材料代替的间隔结构和虚拟栅极结构，其中栅极氧化物结构包括铁电高k材料。

公开(公告)号：US20150200140A1

公开(公告)日：2015-07-16

申请号：US14153521

申请日：2014-01-13

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Sven Beyer ,  Alexander Ebermann ,  Carsten Grass ,  Jan Hoentschel

IPC: H01L21/8234 ,  H01L21/306 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/3065 ,  H01L21/28 ,  H01L21/027 ,  H01L21/02

CPC classification number: H01L21/823431 ,  H01L21/02164 ,  H01L21/02172 ,  H01L21/0275 ,  H01L21/28123 ,  H01L21/28176 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/823437 ,  H01L21/845

Abstract: A method for fabricating an integrated circuit includes providing a semiconductor substrate with a pad layer overlying the semiconductor substrate and a photoresist layer overlying the pad layer, exposing the photoresist layer to a split laser beam to form a plurality of parallel linear void regions in the photoresist layer, and etching the pad layer and the semiconductor substrate beneath the plurality of parallel linear void regions to form a plurality of extended parallel linear void regions. The method further includes depositing a first dielectric material over the semiconductor substrate, patterning a photoresist material over the semiconductor substrate to cover a portion of the semiconductor substrate, and etching portions of the pad layer, the first dielectric material, and the semiconductor substrate. Still further, the method includes depositing a second dielectric material into the second void regions.

Abstract translation: 一种用于制造集成电路的方法包括：提供具有覆盖在半导体衬底上的衬垫层的半导体衬底和覆盖衬垫层的光致抗蚀剂层，将光致抗蚀剂层暴露于分裂激光束以在光刻胶中形成多个平行的线性空隙区域 并且在所述多个平行线性空隙区域下方蚀刻所述衬垫层和所述半导体衬底，以形成多个延伸的平行线性空隙区域。 该方法还包括在半导体衬底上沉积第一介电材料，在半导体衬底上图案化光致抗蚀剂材料以覆盖半导体衬底的一部分，以及蚀刻衬垫层，第一电介质材料和半导体衬底的部分。 此外，该方法包括将第二电介质材料沉积到第二空隙区域中。

公开(公告)号：US08872285B2

公开(公告)日：2014-10-28

申请号：US13781907

申请日：2013-03-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thilo Scheiper ,  Carsten Grass ,  Richard Carter ,  Martin Trentzsch

IPC: H01L21/02 ,  H01L29/78

CPC classification number: H01L21/28185 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7833

Abstract: Disclosed herein are various embodiments of an improved metal gate structure for semiconductor devices, such as transistors. In one example disclosed herein, a transistor has a gate structure consisting of a gate insulation layer positioned on a semiconducting substrate, a high-k insulation layer positioned on the gate insulation layer, a layer of titanium nitride positioned on the high-k insulation layer, a layer of aluminum positioned on the layer of titanium nitride and a layer of polysilicon positioned on the layer of aluminum.

Abstract translation: 这里公开了用于诸如晶体管的半导体器件的改进的金属栅极结构的各种实施例。 在本文公开的一个示例中，晶体管具有由位于半导体衬底上的栅极绝缘层，位于栅极绝缘层上的高k绝缘层，位于高k绝缘层上的氮化钛层组成的栅极结构 ，位于氮化钛层上的铝层和位于铝层上的多晶硅层。

公开(公告)号：US09514942B1

公开(公告)日：2016-12-06

申请号：US15060009

申请日：2016-03-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Thorsten Kammler ,  Andreas Hellmich ,  Carsten Grass

IPC: H01L21/28 ,  H01L21/66 ,  H01L21/311 ,  H01L21/32 ,  H01L27/12

CPC classification number: H01L21/28123 ,  H01L21/32139 ,  H01L21/823437 ,  H01L22/26 ,  H01L27/1207

Abstract: A method of forming a gate structure over a hybrid substrate structure with topography having a bulk region and an SOI region is disclosed including forming a gate material layer above the SOI and bulk regions, forming a mask layer above the gate material layer, forming a first planarization layer above the mask layer, forming a first gate structure masking pattern above the first planarization layer, patterning the first planarization layer in alignment with the first gate structure masking pattern, and patterning the mask layer in accordance with the patterned first planarization layer, resulting in a gate mask disposed above the gate material layer.

Abstract translation: 公开了一种在具有体积区域和SOI区域的形貌的混合衬底结构上形成栅极结构的方法，包括在SOI和体区上形成栅极材料层，在栅极材料层上方形成掩模层，形成第一 在所述掩模层上方形成平坦化层，在所述第一平坦化层上方形成第一栅极结构掩模图案，使与所述第一栅极结构掩模图案对准的所述第一平坦化图案图案化，以及根据所述图案化的第一平坦化层图案化所述掩模层， 在栅极掩模上设置在栅极材料层上方。

公开(公告)号：US20160204218A1

公开(公告)日：2016-07-14

申请号：US14722295

申请日：2015-05-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Carsten Grass ,  Robert Binder ,  Joachim Metzger

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/4966 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/0847 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7848

Abstract: An illustrative method includes providing a semiconductor structure. The semiconductor structure includes an active region and an electrically insulating structure. The active region includes a source region, a channel region and a drain region. The electrically insulating structure includes a recess over the channel region. A work function adjustment layer is deposited over the semiconductor structure. A portion of the work function adjustment layer is deposited at a bottom surface of the recess. The work function adjustment layer includes at least one material other than titanium nitride. A titanium nitride pre-wetting layer is deposited over the work function adjustment layer. A titanium wetting layer is deposited directly on the titanium nitride pre-wetting layer. After the deposition of the titanium wetting layer, the recess is filled with aluminum.

Abstract translation: 一种说明性的方法包括提供半导体结构。 半导体结构包括有源区和电绝缘结构。 有源区包括源极区，沟道区和漏极区。 电绝缘结构包括在通道区域上的凹部。 在半导体结构上沉积功函数调整层。 工作功能调整层的一部分沉积在凹部的底表面。 工作功能调整层包括除了氮化钛之外的至少一种材料。 氮化钛预润湿层沉积在功函数调整层上。 钛润湿层直接沉积在氮化钛预润湿层上。 在沉积钛湿润层之后，凹槽中填充有铝。

公开(公告)号：US20160111549A1

公开(公告)日：2016-04-21

申请号：US14812245

申请日：2015-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Carsten Grass

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/51 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L29/78391 ,  H01L21/28185 ,  H01L21/28291 ,  H01L21/823462 ,  H01L21/823857 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1159 ,  H01L27/11592 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545

Abstract: The present disclosure provides methods of forming a semiconductor circuit element and a semiconductor circuit element, wherein the semiconductor circuit element includes a first semiconductor device with a first gate structure disposed over a first active region of a semiconductor substrate and a second semiconductor device with a second gate structure disposed over a second active region of the semiconductor substrate, the first gate structure comprising a ferroelectric material buried into the first active region before a gate electrode material is formed on the ferroelectric material and the second gate structure comprising a high-k material different from the ferroelectric material.

Abstract translation: 本公开提供了形成半导体电路元件和半导体电路元件的方法，其中半导体电路元件包括具有设置在半导体衬底的第一有源区上的第一栅极结构的第一半导体器件和具有第二半导体元件的第二半导体器件 栅极结构设置在所述半导体衬底的第二有源区上方，所述第一栅极结构包括在栅极电极材料形成在所述铁电材料上之前被埋入所述第一有源区中的铁电材料，并且所述第二栅极结构包括高k材料不同 来自铁电材料。

公开(公告)号：US09123825B2

公开(公告)日：2015-09-01

申请号：US14153521

申请日：2014-01-13

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Sven Beyer ,  Alexander Ebermann ,  Carsten Grass ,  Jan Hoentschel

IPC: H01L21/8234 ,  H01L21/027 ,  H01L21/306 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/3065 ,  H01L21/28 ,  H01L21/311

CPC classification number: H01L21/823431 ,  H01L21/02164 ,  H01L21/02172 ,  H01L21/0275 ,  H01L21/28123 ,  H01L21/28176 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/823437 ,  H01L21/845

Abstract: A method for fabricating an integrated circuit includes providing a semiconductor substrate with a pad layer overlying the semiconductor substrate and a photoresist layer overlying the pad layer, exposing the photoresist layer to a split laser beam to form a plurality of parallel linear void regions in the photoresist layer, and etching the pad layer and the semiconductor substrate beneath the plurality of parallel linear void regions to form a plurality of extended parallel linear void regions. The method further includes depositing a first dielectric material over the semiconductor substrate, patterning a photoresist material over the semiconductor substrate to cover a portion of the semiconductor substrate, and etching portions of the pad layer, the first dielectric material, and the semiconductor substrate. Still further, the method includes depositing a second dielectric material into the second void regions.

Abstract translation: 一种用于制造集成电路的方法包括：提供具有覆盖在半导体衬底上的衬垫层的半导体衬底和覆盖衬垫层的光致抗蚀剂层，将光致抗蚀剂层暴露于分裂激光束以在光刻胶中形成多个平行的线性空隙区域 并且在所述多个平行线性空隙区域下方蚀刻所述衬垫层和所述半导体衬底，以形成多个延伸的平行线性空隙区域。 该方法还包括在半导体衬底上沉积第一介电材料，在半导体衬底上图案化光致抗蚀剂材料以覆盖半导体衬底的一部分，以及蚀刻衬垫层，第一电介质材料和半导体衬底的部分。 此外，该方法包括将第二电介质材料沉积到第二空隙区域中。

公开(公告)号：US20140264626A1

公开(公告)日：2014-09-18

申请号：US14174474

申请日：2014-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Alban Zaka ,  Nicolas Sassiat ,  Jan Hoentschel ,  Martin Trentzsch ,  Carsten Grass

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L21/823462 ,  H01L21/823857 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/7833

Abstract: The present disclosure provides, in some aspects, a gate electrode structure for a semiconductor device. In some illustrative embodiments herein, the gate electrode structure includes a first high-k dielectric layer over a first active region of a semiconductor substrate and a second high-k dielectric layer on the first high-k dielectric layer. The first high-k dielectric layer has a metal species incorporated therein for adjusting the work function of the first high-k dielectric layer.

Abstract translation: 在一些方面，本公开提供了一种用于半导体器件的栅电极结构。 在本文的一些说明性实施例中，栅电极结构包括在半导体衬底的第一有源区上的第一高k电介质层和第一高k电介质层上的第二高k电介质层。 第一高k电介质层具有并入其中的金属物质，用于调节第一高k电介质层的功函数。