公开(公告)号：US20150357409A1

公开(公告)日：2015-12-10

申请号：US14832530

申请日：2015-08-21

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： David V. Horak ,  Shom S. Ponoth ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/417 ,  H01L29/51

CPC classification number: H01L29/0653 ,  H01L21/28008 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes forming a gate structure having a first conductive material above a semiconductor substrate, gate spacers on opposing sides of the first conductive material, and a first interlevel dielectric (ILD) layer surrounding the gate spacers and the first conductive material. An upper portion of the first conductive material is recessed. The gate spacers are recessed until a height of the gate spacers is less than a height of the gate structure. An isolation liner is deposited above the gate spacers and the first conductive material. A portion of the isolation liner is removed so that a top surface of the first conductive material is exposed. A second conductive material is deposited in a contact hole created above the first conductive material and the gate spacers to form a gate contact.

公开(公告)号：US09935168B2

公开(公告)日：2018-04-03

申请号：US15445481

申请日：2017-02-28

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： David V. Horak ,  Shom S. Ponoth ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC: H01L29/06 ,  H01L23/535 ,  H01L29/49 ,  H01L29/423 ,  H01L29/51 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/28008 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes forming a gate structure having a first conductive material above a semiconductor substrate, gate spacers on opposing sides of the first conductive material, and a first interlevel dielectric (ILD) layer surrounding the gate spacers and the first conductive material. An upper portion of the first conductive material is recessed. The gate spacers are recessed until a height of the gate spacers is less than a height of the gate structure. An isolation liner is deposited above the gate spacers and the first conductive material. A portion of the isolation liner is removed so that a top surface of the first conductive material is exposed. A second conductive material is deposited in a contact hole created above the first conductive material and the gate spacers to form a gate contact.

公开(公告)号：US20170170266A1

公开(公告)日：2017-06-15

申请号：US15445481

申请日：2017-02-28

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： David V. Horak ,  Shom S. Ponoth ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC: H01L29/06 ,  H01L29/49 ,  H01L29/78 ,  H01L29/51 ,  H01L29/417 ,  H01L23/535 ,  H01L29/423

CPC classification number: H01L29/0653 ,  H01L21/28008 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes forming a gate structure having a first conductive material above a semiconductor substrate, gate spacers on opposing sides of the first conductive material, and a first interlevel dielectric (ILD) layer surrounding the gate spacers and the first conductive material. An upper portion of the first conductive material is recessed. The gate spacers are recessed until a height of the gate spacers is less than a height of the gate structure. An isolation liner is deposited above the gate spacers and the first conductive material. A portion of the isolation liner is removed so that a top surface of the first conductive material is exposed. A second conductive material is deposited in a contact hole created above the first conductive material and the gate spacers to form a gate contact.

公开(公告)号：US09332628B2

公开(公告)日：2016-05-03

申请号：US14739703

申请日：2015-06-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel C. Edelstein ,  David V. Horak ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  Terry A. Spooner

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H05K1/02 ,  H01L21/768 ,  H05K1/03

CPC classification number: H05K1/0216 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76852 ,  H05K1/0298 ,  H05K1/03 ,  H05K2201/0707 ,  H05K2201/09063

Abstract: A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.

公开(公告)号：US09202879B2

公开(公告)日：2015-12-01

申请号：US13775988

申请日：2013-02-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Charles W. Koburger, III ,  Marc A. Bergendahl ,  David V. Horak ,  Shom Ponoth ,  Chih-Chao Yang

IPC: H01L21/336 ,  H01L29/40 ,  E21B43/30 ,  E21B47/12

CPC classification number: H01L29/401 ,  E21B43/305 ,  E21B47/122 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/845 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/1211

Abstract: In a replacement gate scheme, after formation of a gate dielectric layer, a work function material layer completely fills a narrow gate trench, while not filling a wide gate trench. A dielectric material layer is deposited and planarized over the work function material layer, and is subsequently recessed to form a dielectric material portion overlying a horizontal portion of the work function material layer within the wide gate trench. The work function material layer is recessed employing the dielectric material portion as a part of an etch mask to form work function material portions. A conductive material is deposited and planarized to form gate conductor portions, and a dielectric material is deposited and planarized to form gate cap dielectrics.

Abstract translation: 在替代栅极方案中，在形成栅极电介质层之后，功函数材料层完全填充窄栅极沟槽，同时不填充宽栅极沟槽。 介电材料层在功函数材料层上沉积并平面化，随后凹入以形成覆盖宽栅极沟槽内的功函数材料层的水平部分的介电材料部分。 使用介电材料部分作为蚀刻掩模的一部分来凹入功函数材料层以形成功函数材料部分。 将导电材料沉积并平坦化以形成栅极导体部分，并且沉积和平坦化介电材料以形成栅极盖电介质。

公开(公告)号：US09147576B2

公开(公告)日：2015-09-29

申请号：US14161724

申请日：2014-01-23

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： David V. Horak ,  Shom S. Ponoth ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC: H01L21/336 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L29/0653 ,  H01L21/28008 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes forming a gate structure having a first conductive material above a semiconductor substrate, gate spacers on opposing sides of the first conductive material, and a first interlevel dielectric (ILD) layer surrounding the gate spacers and the first conductive material. An upper portion of the first conductive material is recessed. The gate spacers are recessed until a height of the gate spacers is less than a height of the gate structure. An isolation liner is deposited above the gate spacers and the first conductive material. A portion of the isolation liner is removed so that a top surface of the first conductive material is exposed. A second conductive material is deposited in a contact hole created above the first conductive material and the gate spacers to form a gate contact.

Abstract translation: 形成半导体结构的方法包括在半导体衬底上形成具有第一导电材料的栅极结构，在第一导电材料的相对侧上的栅极间隔物和围绕栅极间隔物的第一层间电介质（ILD）层和第一导电 材料。 第一导电材料的上部是凹进的。 栅极间隔物凹进直到栅极间隔物的高度小于栅极结构的高度。 隔离衬垫沉积在栅极间隔物和第一导电材料上方。 去除隔离衬垫的一部分，使得第一导电材料的顶表面露出。 第二导电材料沉积在形成在第一导电材料和栅极间隔物上方的接触孔中以形成栅极接触。

公开(公告)号：US09263388B2

公开(公告)日：2016-02-16

申请号：US14688027

申请日：2015-04-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L21/44

CPC classification number: H01L23/528 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

Abstract: A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal.

公开(公告)号：US20140339629A1

公开(公告)日：2014-11-20

申请号：US13894513

申请日：2013-05-15

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Shom Ponoth ,  David V. Horak ,  Balasubramanian Pranatharthiharan

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/66666

Abstract: Embodiments of the invention provide approaches for forming gate and source/drain (S/D) contacts. Specifically, the semiconductor device includes a gate transistor formed over a substrate, a S/D contact formed over a trench-silicide (TS) layer and positioned adjacent the gate transistor, and a gate contact formed over the gate transistor, wherein at least a portion of the gate contact is aligned over the TS layer. This structure enables contact with the TS layer, thereby decreasing the distance between the gate contact and the source/drain, which is desirable for ultra-area-scaling.

Abstract translation: 本发明的实施例提供了用于形成栅极和源极/漏极（S / D）触点的方法。 具体地，半导体器件包括形成在衬底上的栅极晶体管，形成在沟槽硅化物（TS）层上并且邻近栅极晶体管定位的S / D接触，以及形成在栅极晶体管上的栅极接触，其中至少一个 栅极触点的一部分在TS层上对齐。 这种结构使得能够与TS层接触，从而减小栅极接触和源极/漏极之间的距离，这对于超区域缩放是期望的。

公开(公告)号：US20160260812A1

公开(公告)日：2016-09-08

申请号：US15153249

申请日：2016-05-12

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： David V. Horak ,  Shom S. Ponoth ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/417 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/0653 ,  H01L21/28008 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes forming a gate structure having a first conductive material above a semiconductor substrate, gate spacers on opposing sides of the first conductive material, and a first interlevel dielectric (ILD) layer surrounding the gate spacers and the first conductive material. An upper portion of the first conductive material is recessed. The gate spacers are recessed until a height of the gate spacers is less than a height of the gate structure. An isolation liner is deposited above the gate spacers and the first conductive material. A portion of the isolation liner is removed so that a top surface of the first conductive material is exposed. A second conductive material is deposited in a contact hole created above the first conductive material and the gate spacers to form a gate contact.

公开(公告)号：US09379198B2

公开(公告)日：2016-06-28

申请号：US14494699

申请日：2014-09-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chih-Chao Yang ,  David V. Horak ,  Charles W. Koburger ,  Shom Ponoth

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L29/42372 ,  H01L21/28247 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76856 ,  H01L21/76888 ,  H01L21/76897 ,  H01L29/495 ,  H01L29/517 ,  H01L29/78

Abstract: An integrated circuit structure with a selectively formed and at least partially oxidized metal cap over a gate. In one embodiment, an integrated circuit structure has: a substrate; a metal gate located over the substrate; at least one liner layer over the substrate and substantially surrounding the metal gate; and an at least partially oxidized etch stop layer located directly over the metal gate, the etch stop layer including at least one of cobalt (Co), manganese (Mn), tungsten (W), iridium (Ir), rhodium (Rh) or ruthenium (Ru).

Abstract translation: 一种在栅极上具有选择性地形成和至少部分氧化的金属盖的集成电路结构。 在一个实施例中，集成电路结构具有：基板; 位于衬底上方的金属栅极; 至少一个衬底层，并且基本上围绕着金属栅极; 以及位于金属栅极正上方的至少部分氧化的蚀刻停止层，所述蚀刻停止层包括钴（Co），锰（Mn），钨（W），铱（Ir），铑（Rh）或 钌（Ru）。