公开(公告)号：US20160064123A1

公开(公告)日：2016-03-03

申请号：US14469012

申请日：2014-08-26

Applicant: Globalfoundries Inc.

Inventor： Stefan Flachowsky ,  Ralf Illgen ,  Jan Hoentschel

IPC: H01C1/16 ,  H01C17/075 ,  H01C7/18 ,  H01C7/00 ,  H01C7/02 ,  H01C7/04

CPC classification number: H01C1/16 ,  H01C7/008 ,  H01C7/021 ,  H01C7/027 ,  H01C7/041 ,  H01C17/075

Abstract: The present disclosure relates to a semiconductor structure comprising a positive temperature coefficient thermistor and a negative temperature coefficient thermistor, connected to each other in parallel by means of connecting elements which are configured such that the resistance resulting from the parallel connection is substantially stable in a predetermined temperature range, and to a corresponding manufacturing method.

Abstract translation: 本公开内容涉及包括正温度系数热敏电阻和负温度系数热敏电阻的半导体结构，该正温度系数热敏电阻和负温度系数热敏电阻通过连接元件彼此并联连接，连接元件被构造成使得由并联连接产生的电阻在预定的 温度范围和相应的制造方法。

公开(公告)号：US09269714B2

公开(公告)日：2016-02-23

申请号：US13914288

申请日：2013-06-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Illgen ,  Gerd Zschaezsch

IPC: H01L21/84 ,  H01L27/092 ,  H01L21/8238 ,  H01L27/12

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203

Abstract: A device includes a substrate, a P-channel transistor and an N-channel transistor. The substrate includes a first layer of a first semiconductor material and a second layer of a second semiconductor material. The first and second semiconductor materials have different crystal lattice constants. The P-channel transistor includes a channel region having a compressive stress in a first portion of the substrate. The channel region of the P-channel transistor includes a portion of the first layer of the first semiconductor material and a portion of the second layer of the second semiconductor material. The N-channel transistor includes a channel region having a tensile stress formed in a second portion of the substrate. The channel region of the N-channel transistor includes a portion of the first layer of the first semiconductor material and a portion of the second layer of the second semiconductor material. Methods of forming the device are also disclosed.

Abstract translation: 一种器件包括衬底，P沟道晶体管和N沟道晶体管。 衬底包括第一半导体材料的第一层和第二半导体材料的第二层。 第一和第二半导体材料具有不同的晶格常数。 P沟道晶体管包括在衬底的第一部分中具有压应力的沟道区。 P沟道晶体管的沟道区域包括第一半导体材料的第一层的一部分和第二半导体材料的第二层的一部分。 N沟道晶体管包括在衬底的第二部分中形成的具有拉伸应力的沟道区。 N沟道晶体管的沟道区域包括第一半导体材料的第一层的一部分和第二半导体材料的第二层的一部分。 还公开了形成装置的方法。

公开(公告)号：US20140246696A1

公开(公告)日：2014-09-04

申请号：US13783547

申请日：2013-03-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stefan Flachowsky ,  Roman Boschke ,  Ralf Illgen

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

Abstract: When forming sophisticated semiconductor devices including N-channel transistors with strain-inducing embedded source and drain semiconductor regions, N-channel transistor performance may be enhanced by selectively growing embedded pure silicon source and drain regions in cavities exposing the silicon/germanium layer of a Si/SiGe-substrate, wherein the silicon layer of the Si/SiGe-substrate may exhibit a strong bi-axial tensile strain. The bi-axial tensile strain may improve both electron and hole mobility.

Abstract translation: 当形成包括具有应变诱导嵌入式源极和漏极半导体区域的N沟道晶体管的复杂半导体器件时，可以通过选择性地生长暴露硅/锗层中的嵌入式纯硅源极和漏极区域来增强N沟道晶体管性能 / SiGe衬底，其中Si / SiGe衬底的硅层可能表现出强的双轴向拉伸应变。 双轴拉伸应变可以改善电子和空穴迁移率。

公开(公告)号：US20170025442A1

公开(公告)日：2017-01-26

申请号：US14805827

申请日：2015-07-22

Applicant: GLOBALFOUNDRIES Inc

Inventor： Stefan Flachowsky ,  Ralf Illgen

IPC: H01L27/12 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/324 ,  H01L21/3213 ,  H01L29/78 ,  H01L21/265 ,  H01L21/84 ,  H01L29/66 ,  H01L21/308

CPC classification number: H01L27/1207 ,  H01L21/26513 ,  H01L21/308 ,  H01L21/31051 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/84 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833

Abstract: A method includes providing a semiconductor-on-insulator structure including a semiconductor substrate, a layer of electrically insulating material over the semiconductor substrate and a layer of semiconductor material over the layer of electrically insulating material. A first transistor is formed. The formation of the first transistor includes forming a dummy gate structure over the layer of semiconductor material, forming a source region of the first transistor and a drain region of the first transistor in portions of the semiconductor substrate adjacent the dummy gate structure, forming an electrically insulating structure annularly enclosing the dummy gate structure and performing a replacement gate process. The replacement gate process includes removing the dummy gate structure and a portion of the layer of semiconductor material below the dummy gate structure, wherein a recess is formed in the electrically insulating structure. The recess is filled with an electrically conductive material.

Abstract translation: 一种方法包括提供包括半导体衬底，半导体衬底上的电绝缘材料层和电绝缘材料层上的半导体材料层的绝缘体上半导体结构。 形成第一晶体管。 第一晶体管的形成包括在半导体材料层上形成虚拟栅极结构，在与半栅极结构相邻的半导体衬底的部分中形成第一晶体管的源极区域和第一晶体管的漏极区域，形成电气 绝缘结构环形地包围虚拟栅极结构并执行替换栅极工艺。 替代栅极工艺包括在虚拟栅极结构下方去除伪栅极结构和半导体材料层的一部分，其中在电绝缘结构中形成凹部。 凹部填充有导电材料。

公开(公告)号：US20160358915A1

公开(公告)日：2016-12-08

申请号：US15238023

申请日：2016-08-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Illgen ,  Jan Hoentschel

IPC: H01L27/088 ,  H01L27/11 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/28291 ,  H01L21/823431 ,  H01L21/823462 ,  H01L29/42364 ,  H01L29/512 ,  H01L29/516 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66553 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor substrate and a fin positioned above the semiconductor substrate, wherein the fin includes a semiconductor material. Additionally, a ferroelectric high-k spacer covers sidewall surfaces of the fin and a non-ferroelectric high-k material layer covers the ferroelectric high-k spacer and the fin, wherein a portion of the non-ferroelectric high-k material layer is positioned on and in direct contact with the semiconductor material at the upper surface of the fin.

Abstract translation: 半导体器件包括位于半导体衬底之上的半导体衬底和鳍，其中鳍包括半导体材料。 此外，铁电高k隔板覆盖翅片的侧壁表面，并且非铁电高k材料层覆盖铁电高k隔板和翅片，其中非铁电高k材料层的一部分被定位 在鳍的上表面上与半导体材料直接接触。

公开(公告)号：US08835936B2

公开(公告)日：2014-09-16

申请号：US13678124

申请日：2012-11-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Ralf Illgen

IPC: H01L29/15 ,  H01L31/0312 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L21/2257 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/66545 ,  H01L29/66628

Abstract: A method comprises providing a semiconductor structure comprising a substrate, an electrically insulating layer on the substrate and a semiconductor feature on the electrically insulating layer. A gate structure is formed on the semiconductor feature. An in situ doped semiconductor material is deposited on portions of the semiconductor feature adjacent the gate structure. Dopant is diffused from the in situ doped semiconductor material into the portions of the semiconductor feature adjacent the gate structure, the diffusion of the dopant into the portions of the semiconductor feature adjacent the gate structure forming doped source and drain regions in the semiconductor feature.

Abstract translation: 一种方法包括提供包括衬底，在衬底上的电绝缘层和电绝缘层上的半导体特征的半导体结构。 在半导体特征上形成栅极结构。 原位掺杂的半导体材料沉积在与栅极结构相邻的半导体器件的部分上。 掺杂剂从原位掺杂的半导体材料扩散到与栅极结构相邻的半导体器件的部分，掺杂剂扩散到半导体器件的与栅极结构相邻的部分，形成半导体器件中的掺杂源极和漏极区。

公开(公告)号：US20140027825A1

公开(公告)日：2014-01-30

申请号：US14039450

申请日：2013-09-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tim Baldauf ,  Andy Wei ,  Tom Herrmann ,  Stefan Flachowsky ,  Ralf Illgen

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L27/0886

Abstract: When forming sophisticated multiple gate transistors and planar transistors in a common manufacturing sequence, the threshold voltage characteristics of the multiple gate transistors may be intentionally “degraded” by selectively incorporating a dopant species into corner areas of the semiconductor fins, thereby obtaining a superior adaptation of the threshold voltage characteristics of multiple gate transistors and planar transistors. In advantageous embodiments, the incorporation of the dopant species may be accomplished by using the hard mask, which is also used for patterning the self-aligned semiconductor fins.

Abstract translation: 当在共同的制造顺序中形成复杂的多栅极晶体管和平面晶体管时，通过选择性地将掺杂剂物质结合到半导体鳍片的角区域中，可以有意地“降低”多个栅极晶体管的阈值电压特性，从而获得 多个栅极晶体管和平面晶体管的阈值电压特性。 在有利的实施方案中，可以通过使用硬掩模来实现掺杂物种的掺入，该硬掩模也用于图案化自对准半导体鳍片。

公开(公告)号：US09966466B2

公开(公告)日：2018-05-08

申请号：US15231105

申请日：2016-08-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Illgen

IPC: H01L21/02 ,  H01L29/78 ,  H01L21/28 ,  H01L21/762 ,  H01L21/324 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7849 ,  H01L21/02181 ,  H01L21/02356 ,  H01L21/28291 ,  H01L21/324 ,  H01L21/76251 ,  H01L21/76254 ,  H01L29/66742 ,  H01L29/786 ,  H01L29/78654

Abstract: A semiconductor-on-insulator wafer includes a support substrate, an electrically insulating layer over the support substrate and a semiconductor layer over the electrically insulating layer. A semiconductor structure includes a transistor. The transistor includes an electrically insulating layer including a piezoelectric material over a support substrate, a semiconductor layer over the electrically insulating layer, a source region, a channel region and a drain region in the semiconductor layer, a gate structure over the channel region, a first electrode and a second electrode. The first electrode and the second electrode are provided at laterally opposite sides of the electrically insulating layer. The first and second electrodes are electrically insulated from the semiconductor layer and configured for applying a voltage to the piezoelectric material of the electrically insulating layer. The piezoelectric material creates a strain at least in the channel region in response to the voltage applied thereto.

公开(公告)号：US20170338350A1

公开(公告)日：2017-11-23

申请号：US15234361

申请日：2016-08-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Illgen

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L21/266 ,  H01L29/08 ,  H01L21/3115 ,  H01L21/28 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/78391 ,  H01L21/02181 ,  H01L21/02321 ,  H01L21/266 ,  H01L21/28185 ,  H01L21/31155 ,  H01L29/0847 ,  H01L29/40111 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/512 ,  H01L29/516 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6684

Abstract: The present disclosure provides a semiconductor device including a substrate, a gate structure formed over the substrate, the gate structure including a first ferroelectric material having a first remanent polarization and a second ferroelectric material having a second remanent polarization, the first remanent polarization being smaller than the second remanent polarization, and source and drain regions formed in the substrate, the source and drain regions being laterally separated by a channel region extending along a length direction below the gate structure, wherein the first ferroelectric material and the second ferroelectric material are stacked in a plane parallel to an upper surface of the substrate.

公开(公告)号：US20170200743A1

公开(公告)日：2017-07-13

申请号：US15467305

申请日：2017-03-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Illgen

IPC: H01L27/12 ,  H01L21/308 ,  H01L21/3105 ,  H01L29/78 ,  H01L21/324 ,  H01L21/84 ,  H01L29/06 ,  H01L29/66 ,  H01L21/265 ,  H01L21/3213

CPC classification number: H01L27/1207 ,  H01L21/26513 ,  H01L21/308 ,  H01L21/31051 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/84 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833

Abstract: A semiconductor structure includes a semiconductor substrate, a layer of electrically insulating material above the semiconductor substrate, and a layer of semiconductor material above the layer of electrically insulating material. A first transistor includes a first source region, a first drain region, and a first channel region formed in the semiconductor substrate, a first gate insulation layer positioned above the first channel region, and an electrically conductive first gate electrode, wherein the first gate insulation layer includes a first portion of the electrically insulating material. A second transistor includes a second source region, a second drain region, and a second channel region formed in the layer of semiconductor material, a second gate insulation layer positioned above the second channel region, and an electrically conductive second gate electrode, wherein a second portion of the layer of electrically insulating material is positioned below the second channel region.