公开(公告)号：US20200105886A1

公开(公告)日：2020-04-02

申请号：US16149711

申请日：2018-10-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hong ,  Hui Zang ,  Hsien-Ching Lo

IPC: H01L29/417 ,  H01L27/12 ,  H01L29/06 ,  H01L21/84 ,  H01L21/02 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/08 ,  H01L21/762 ,  H01L21/027

Abstract: Structures for a field-effect transistor and methods for fabricating a structure for a field-effect transistor. First and second device structure are respectively formed in first and second device regions, and a first dielectric layer is formed over the first and second device regions. The first dielectric layer includes a recess defining a step at a transition between the first and second device regions, and a second dielectric layer is arranged within the recess in the first dielectric layer. A third dielectric layer is arranged over the first dielectric layer in the first device region and over the second dielectric layer in the second device region. A contact, which is coupled with the second device structure, extends through the first, second, and third dielectric layers in the second device region.

公开(公告)号：US20200043779A1

公开(公告)日：2020-02-06

申请号：US16052085

申请日：2018-08-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hong ,  Liu Jiang ,  Yongjun Shi ,  Yi Qi ,  Hsien-Ching Lo ,  Hui Zang

IPC: H01L21/768 ,  H01L27/12 ,  H01L29/66 ,  H01L21/84 ,  H01L21/28

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A first dielectric layer is deposited over a first gate structure in a first device area and a second gate structure in a second device area, and then planarized. A second dielectric layer is deposited over the planarized first dielectric layer, and then removed from the first device area. After removing the second dielectric layer from the first device area, the first dielectric layer in the first device area is recessed to expose the first gate structure. A silicide is formed on the exposed first gate structure.

公开(公告)号：US10396206B2

公开(公告)日：2019-08-27

申请号：US15643940

申请日：2017-07-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ashish Kumar Jha ,  Haiting Wang ,  Wei Hong ,  Wei Zhao ,  Tae Jeong Lee ,  Zhenyu Hu

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/033 ,  H01L21/02 ,  H01L21/027 ,  H01L21/321 ,  H01L21/3105 ,  H01L21/3205 ,  H01L29/66 ,  H01L21/475 ,  H01L29/43 ,  H01L27/02 ,  H01L27/118

Abstract: A method of manufacturing a semiconductor device includes the formation of an oxide spacer layer to modify the critical dimension of a gate cut opening in connection with a replacement metal gate process. The oxide spacer layer is deposited after etching a gate cut opening in an overlying hard mask such that the oxide spacer layer is deposited onto sidewall surfaces of the hard mask within the opening and directly over the top surface of a sacrificial gate. The oxide spacer may also be deposited into recessed regions within an interlayer dielectric located adjacent to the sacrificial gate. By filling the recessed regions with an oxide, the opening of trenches through the oxide spacer layer and the interlayer dielectric to expose source/drain junctions can be simplified.

公开(公告)号：US10068902B1

公开(公告)日：2018-09-04

申请号：US15715220

申请日：2017-09-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanping Shen ,  Hui Zang ,  Hsien-Ching Lo ,  Yongjun Shi ,  Randy W. Mann ,  Yi Qi ,  Guowei Xu ,  Wei Hong ,  Jerome Ciavatti ,  Jae Gon Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/11 ,  H01L29/06 ,  H01L29/66

Abstract: Disclosed is a method of forming an integrated circuit (IC) structure with multiple non-planar transistors having different effective channel widths. In the method, sacrificial gates are removed from partially completed transistors, creating gate openings that expose sections of semiconductor fins between source/drain regions. Prior to forming replacement metal gates in the gate openings, additional process steps are performed so that, in the resulting IC structure, some transistors have different channel region heights and, thereby different effective channel widths, than others. These steps can include forming isolation regions in the bottoms of some gate openings. Additionally or alternatively, these steps can include filling some gate openings with a sacrificial material, recessing the sacrificial material to expose fin tops within those gate openings, either recessing the fin tops or forming isolation regions in the fin tops, and removing the sacrificial material. Also disclosed is an IC structure formed according to the method.

公开(公告)号：US10756184B2

公开(公告)日：2020-08-25

申请号：US16180486

申请日：2018-11-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： George R. Mulfinger ,  Timothy J. McArdle ,  Judson R. Holt ,  Steffen A. Sichler ,  Ömür I. Aydin ,  Wei Hong ,  Yi Qi ,  Hui Zang ,  Liu Jiang

IPC: H01L29/08 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L21/28

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to faceted epitaxial source/drain regions and methods of manufacture. The structure includes: a gate structure over a substrate; an L-shaped sidewall spacer located on sidewalls of the gate structure and extending over the substrate adjacent to the gate structure; and faceted diffusion regions on the substrate, adjacent to the L-shaped sidewall spacer.

公开(公告)号：US10546775B1

公开(公告)日：2020-01-28

申请号：US16052085

申请日：2018-08-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hong ,  Liu Jiang ,  Yongjun Shi ,  Yi Qi ,  Hsien-Ching Lo ,  Hui Zang

IPC: H01L21/70 ,  H01L21/768 ,  H01L27/12 ,  H01L29/66 ,  H01L21/28 ,  H01L21/84 ,  H01L21/762 ,  H01L29/78

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A first dielectric layer is deposited over a first gate structure in a first device area and a second gate structure in a second device area, and then planarized. A second dielectric layer is deposited over the planarized first dielectric layer, and then removed from the first device area. After removing the second dielectric layer from the first device area, the first dielectric layer in the first device area is recessed to expose the first gate structure. A silicide is formed on the exposed first gate structure.

公开(公告)号：US10461155B2

公开(公告)日：2019-10-29

申请号：US15811990

申请日：2017-11-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yoong Hooi Yong ,  Yanping Shen ,  Hsien-Ching Lo ,  Xusheng Wu ,  Joo Tat Ong ,  Wei Hong ,  Yi Qi ,  Dongil Choi ,  Yongjun Shi ,  Alina Vinslava ,  James Psillas ,  Hui Zang

IPC: H01L29/08 ,  H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165

Abstract: A semiconductor structure including a source/drain region is disclosed. The source/drain region may include a first epitaxial region along at least one sidewall of the source/drain region having a substantially uniform sidewall thickness. The semiconductor structure may further include a gate structure adjacent and above the source/drain region wherein at least a portion of the first epitaxial region is positioned below a sidewall spacer of the gate structure. A method of forming a source/drain region including a first epitaxial region having a substantially uniform sidewall thickness is disclosed. The method may include forming a trench in a substrate adjacent to a gate structure, forming the first epitaxial region in the trench, forming a spacer material layer on the gate structure and on a portion of the first epitaxial region, and removing a portion of the first epitaxial region using the spacer material layer as a mask.

公开(公告)号：US20190312117A1

公开(公告)日：2019-10-10

申请号：US15949730

申请日：2018-04-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Hsien-Ching Lo ,  Hong Yu ,  Yanping Shen ,  Wei Hong ,  Xing Zhang ,  Ruilong Xie ,  Haiting Wang ,  Hui Zhan ,  Yong Jun Shi

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/45 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02

Abstract: One illustrative FinFET device disclosed herein includes a source/drain structure that, when viewed in a cross-section taken through the fin in a direction corresponding to the gate width (GW) direction of the device, comprises a perimeter and a bottom surface. The source/drain structure also has an axial length that extends in a direction corresponding to the gate length (GL) direction of the device. The device also includes a metal silicide material positioned on at least a portion of the perimeter of the source/drain structure for at least a portion of the axial length of the source/drain structure and on at least a portion of the bottom surface of the source/drain structure for at least a portion of the axial length of the source/drain structure.

公开(公告)号：US20190103319A1

公开(公告)日：2019-04-04

申请号：US15723472

申请日：2017-10-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yi Qi ,  Hsien-Ching Lo ,  Jianwei Peng ,  Wei Hong ,  Yanping Shen ,  Yongjun Shi ,  Hui Zang ,  Ruilong Xie ,  Kangguo Cheng ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/3213 ,  H01L27/088

Abstract: Disclosed is a method of forming a structure with multiple vertical field effect transistors (VFETs). In the method, lower source/drain regions are formed on a substrate such that semiconductor fins extend vertically above the lower source/drain regions. Lower spacers are formed on the lower source/drain regions and positioned laterally adjacent to the semiconductor fins. Gates, having co-planar top surfaces, are formed on the lower spacers and positioned laterally adjacent to the semiconductor fins. However, process steps are performed prior to gate formation to ensure that the top surfaces of the lower source/drain region and lower spacer of a first VFET are below the levels of the top surfaces of the lower source/drain region and lower spacer, respectively, of a second VFET. As a result, the first VFET will have a longer gate, higher threshold voltage and lower switching speed. Also disclosed is the structure formed according to the method.

公开(公告)号：US10249538B1

公开(公告)日：2019-04-02

申请号：US15723472

申请日：2017-10-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yi Qi ,  Hsien-Ching Lo ,  Jianwei Peng ,  Wei Hong ,  Yanping Shen ,  Yongjun Shi ,  Hui Zang ,  Ruilong Xie ,  Kangguo Cheng ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/3213 ,  H01L21/311

Abstract: Disclosed is a method of forming a structure with multiple vertical field effect transistors (VFETs). In the method, lower source/drain regions are formed on a substrate such that semiconductor fins extend vertically above the lower source/drain regions. Lower spacers are formed on the lower source/drain regions and positioned laterally adjacent to the semiconductor fins. Gates, having co-planar top surfaces, are formed on the lower spacers and positioned laterally adjacent to the semiconductor fins. However, process steps are performed prior to gate formation to ensure that the top surfaces of the lower source/drain region and lower spacer of a first VFET are below the levels of the top surfaces of the lower source/drain region and lower spacer, respectively, of a second VFET. As a result, the first VFET will have a longer gate, higher threshold voltage and lower switching speed. Also disclosed is the structure formed according to the method.