中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

44 records (took 0.015 seconds)

    Methods of removing fins so as to form isolation structures on products that include FinFET semiconductor devices
    13.
    发明授权
    Methods of removing fins so as to form isolation structures on products that include FinFET semiconductor devices 有权
    去除鳍片以便在包括FinFET半导体器件的产品上形成隔离结构的方法

    公开(公告)号：US09455198B1

    公开(公告)日：2016-09-27

    申请号：US14676034

    申请日：2015-04-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Hong Yu ,  HongLiang Shen ,  Zhenyu Hu ,  Lun Zhao ,  Richard J. Carter ,  Xusheng Wu

    IPC: H01L21/8234 ,  H01L21/308

    CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/66

    Abstract: One illustrative method disclosed herein includes, among other things, removing at least one, but not all, of a plurality of first features in a first patterned mask layer so as to define a modified first patterned masking layer, wherein removed first feature(s) correspond to a location where a final isolation structure will be formed, performing an etching process though the modified first patterned masking layer to form an initial isolation trench in the substrate, and performing another etching process through the modified first patterned mask layer to thereby define a plurality of fin-formation trenches in the substrate and to extend a depth of the initial isolation trench so as to define a final isolation trench for the final isolation structure.

    Abstract translation: 本文公开的一种说明性方法包括除去第一图案化掩模层中的多个第一特征中的至少一个但不是全部的，以便限定经修改的第一图案化掩模层，其中去除的第一特征 对应于将形成最终隔离结构的位置，通过经修改的第一图案化掩模层执行蚀刻工艺，以在衬底中形成初始隔离沟槽，以及通过修改的第一图案化掩模层执行另一蚀刻工艺，由此限定 在衬底中的多个翅片形成沟槽并且延伸初始隔离沟槽的深度，以便限定用于最终隔离结构的最终隔离沟槽。

    Uniform exposed raised structures for non-planar semiconductor devices
    14.
    发明授权
    Uniform exposed raised structures for non-planar semiconductor devices 有权
    用于非平面半导体器件的均匀暴露的凸起结构

    公开(公告)号：US09362176B2

    公开(公告)日：2016-06-07

    申请号：US14319640

    申请日：2014-06-30

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Hong Yu ,  HongLiang Shen ,  Zhao Lun ,  Zhenyu Hu ,  Richard J. Carter

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L21/762 ,  H01L21/306

    CPC classification number: H01L21/823481 ,  H01L21/30604 ,  H01L21/762 ,  H01L21/76229 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0653

    Abstract: The use of two different materials for shallow trench isolation and deep structural trenches with a dielectric material therein (e.g., flowable oxide and a HARP oxide, respectively) causes non-uniform heights of exposed portions of raised semiconductor structures for non-planar semiconductor devices, due to the different etch rates of the materials. Non-uniform openings adjacent the exposed portions of the raised structures from recessing the isolation and dielectric materials are filled with additional dielectric material to create a uniform top layer of one material (the dielectric material), which can then be uniformly recessed to expose uniform portions of the raised structures.

    Abstract translation: 对于浅沟槽隔离和其中具有介电材料的深结构沟槽（例如，可流动的氧化物和HARP氧化物）分别使用两种不同的材料导致用于非平面半导体器件的凸起半导体结构的暴露部分的不均匀高度， 由于材料的蚀刻速率不同。 与凸起结构的暴露部分相邻的不均匀的开口不会使隔离和介电材料凹陷，填充有额外的电介质材料，以形成均匀的一层材料（电介质材料）的顶层，然后可将其均匀地凹入以露出均匀的部分 的凸起结构。

    Epitaxial block layer for a fin field effect transistor device
    15.
    发明授权
    Epitaxial block layer for a fin field effect transistor device 有权
    翅片场效应晶体管器件的外延阻挡层

    公开(公告)号：US09293586B2

    公开(公告)日：2016-03-22

    申请号：US13944048

    申请日：2013-07-17

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Zhenyu Hu ,  Richard J. Carter ,  Andy Wei ,  Qi Zhang ,  Sruthi Muralidharan ,  Amy L. Child

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/7848 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/24 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

    Abstract: Approaches for enabling uniform epitaxial (epi) growth in an epi junction area of a semiconductor device (e.g., a fin field effect transistor device) are provided. Specifically, a semiconductor device is provided including a dummy gate and a set of fin field effect transistors (FinFETs) formed over a substrate; a spacer layer formed over the dummy gate and each of the set of FinFETs; and an epi material formed within a set of recesses in the substrate, the set of recesses formed prior to removal of an epi block layer over the dummy gate.

    Abstract translation: 提供了在半导体器件（例如，鳍式场效应晶体管器件）的外延连接区域中实现均匀外延（epi）生长的方法。 具体地说，提供了一种半导体器件，包括形成在衬底上的伪栅极和一组鳍状场效应晶体管（FinFET）; 形成在所述伪栅极和所述一组FinFET中的每一个上的间隔层; 以及形成在衬底中的一组凹部内的外延材料，该组凹陷在去除伪栅极之前的外延阻挡层之前形成。

    Uniform gate height for semiconductor structure with N and P type fins
    17.
    发明授权
    Uniform gate height for semiconductor structure with N and P type fins 有权
    具有N型和P型翅片的半导体结构的均匀栅极高度

    公开(公告)号：US08987083B1

    公开(公告)日：2015-03-24

    申请号：US14202985

    申请日：2014-03-10

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Zhenyu Hu ,  Zhao Lun ,  Xing Zhang

    IPC: H01L21/8238 ,  H01L27/108 ,  H01L29/76 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L29/06

    CPC classification number: H01L29/0657 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66545

    Abstract: In a non-planar based semiconductor process where the structure includes both N and P type raised structures (e.g., fins), and where a different type of epitaxy is to be grown on each of the N and P type raised structures, prior to the growing, a lithographic blocking material over one of the N and P type raised structure portions is selectively etched to expose and planarize a gate cap. After the first type of epitaxy is grown, the process is repeated for the other of the N and P type epitaxy.

    Abstract translation: 在非平面型半导体工艺中，其结构包括N型和P型凸起结构（例如翅片），并且其中不同类型的外延将在N型和P型凸起结构中的每一种上生长，在 选择性地蚀刻在N型和P型凸起结构部分之上的平版印刷阻挡材料以暴露和平坦化栅极盖。 在第一种类型的外延生长之后，对于N和P型外延中的另一种重复该过程。

Patent Agency Ranking