公开(公告)号：US09548312B1

公开(公告)日：2017-01-17

申请号：US14937041

申请日：2015-11-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sven Beyer ,  Alexander Ebermann ,  Martin Schulze

IPC: H01L21/4763 ,  H01L27/115 ,  H01L21/28

CPC classification number: H01L27/11524 ,  H01L21/28273 ,  H01L27/11536 ,  H01L27/11539

Abstract: A method includes providing a semiconductor structure including a nonvolatile memory cell element and one or more electrically insulating layers covering the nonvolatile memory cell element. The nonvolatile memory cell element includes a source region, a channel region, a drain region and a floating gate over at least a first portion of the channel region. A first opening is formed in the electrically insulating layers over the floating gate, a control gate insulation layer is deposited, and a second opening is formed in the electrically insulating layers over the drain region. The first opening and the second opening are filled with an electrically conductive material. The electrically conductive material in the first opening provides a control gate of the nonvolatile memory cell element and the electrically conductive material in the second opening provides an electrical contact to the drain region.

Abstract translation: 一种方法包括提供包括非易失性存储单元元件和覆盖非易失性存储单元元件的一个或多个电绝缘层的半导体结构。 非易失性存储单元元件包括在沟道区的至少第一部分上的源极区，沟道区，漏极区和浮置栅极。 在浮置栅极上的电绝缘层中形成第一开口，沉积控制栅极绝缘层，并且在漏极区域上的电绝缘层中形成第二开口。 第一开口和第二开口填充有导电材料。 第一开口中的导电材料提供非易失性存储单元元件的控制栅极，并且第二开口中的导电材料提供与漏极区域的电接触。

公开(公告)号：US20160141393A1

公开(公告)日：2016-05-19

申请号：US15003370

申请日：2016-01-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Andreas Kurz ,  Sven Beyer ,  Wolfgang Buchholtz

IPC: H01L29/66 ,  H01L21/308 ,  H01L49/02 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/308 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0629 ,  H01L27/0738 ,  H01L28/20 ,  H01L29/66545

Abstract: A method includes forming a plurality of fins in a semiconductor substrate using a common patterning process. A conductive layer is formed above the plurality of fins. A mask is formed above the conductive layer. The conductive layer is etched using the mask to define trenches in the conductive layer. A first insulating layer is formed above the conductive layer and in the trenches. First and second contacts are formed connected to respective ends of the conductive layer.

Abstract translation: 一种方法包括使用共同的图案化工艺在半导体衬底中形成多个翅片。 在多个翅片上方形成导电层。 在导电层上方形成掩模。 使用掩模蚀刻导电层以在导电层中限定沟槽。 第一绝缘层形成在导电层上方和沟槽中。 第一和第二触点形成为连接到导电层的相应末端。

公开(公告)号：US08815741B1

公开(公告)日：2014-08-26

申请号：US13793082

申请日：2013-03-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Jan Hoentschel ,  Sven Beyer ,  Peter Javorka

IPC: H01L21/311 ,  H01L21/265

CPC classification number: H01L21/265 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/31155 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

Abstract: A method includes providing a semiconductor structure including a substrate and a transistor element. A layer of a spacer material is deposited over the substrate and the gate structure, wherein the deposited layer of spacer material has an intrinsic stress. Ions are implanted into the layer of spacer material. After the deposition of the layer of spacer material and the implantation of ions into the layer of spacer material, a sidewall spacer is formed at sidewalls of the gate structure from the layer of spacer material.

Abstract translation: 一种方法包括提供包括衬底和晶体管元件的半导体结构。 在衬底和栅极结构上沉积间隔材料层，其中间隔物材料的沉积层具有固有应力。 离子被植入到间隔物材料层中。 在间隔物材料层沉积并将离子注入到间隔物材料层中之后，在间隔物材料层的栅极结构的侧壁处形成侧壁间隔物。

公开(公告)号：US20140113455A1

公开(公告)日：2014-04-24

申请号：US13655844

申请日：2012-10-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Berthold Reimer ,  Johannes von Kluge ,  Sven Beyer

IPC: H01L21/306

CPC classification number: H01L29/6656 ,  H01L21/0206 ,  H01L21/28052 ,  H01L21/31111 ,  H01L29/665 ,  H01L29/7833

Abstract: A method disclosed herein includes providing a semiconductor structure comprising a transistor, the transistor comprising a gate electrode and a silicon nitride sidewall spacer formed at the gate electrode. A wet etch process is performed. The wet etch process removes at least a portion of the silicon nitride sidewall spacer. The wet etch process comprises applying an etchant comprising at least one of hydrofluoric acid and phosphoric acid.

Abstract translation: 本文公开的方法包括提供包括晶体管的半导体结构，所述晶体管包括形成在栅极处的栅电极和氮化硅侧壁间隔物。 执行湿蚀刻工艺。 湿蚀刻工艺去除氮化硅侧壁间隔物的至少一部分。 湿蚀刻工艺包括施加包含氢氟酸和磷酸中的至少一种的蚀刻剂。

公开(公告)号：US10163933B1

公开(公告)日：2018-12-25

申请号：US15676529

申请日：2017-08-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Stefan Dünkel ,  Martin Trentzsch ,  Sven Beyer

IPC: H01L29/10 ,  H01L29/76 ,  H01L31/036 ,  H01L31/112 ,  H01L27/1159 ,  H01L27/11597 ,  H01L29/16 ,  H01L29/04 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L21/28 ,  H01L29/51

Abstract: Methods of forming a buffer layer to imprint ferroelectric phase in a ferroelectric layer and the resulting devices are provided. Embodiments include forming a substrate; forming a buffer layer over the substrate; forming a ferroelectric layer over the buffer layer; forming a channel layer over the ferroelectric layer; forming a gate oxide layer over a portion of the channel layer; and forming a gate over the gate oxide layer.

公开(公告)号：US10084057B2

公开(公告)日：2018-09-25

申请号：US15237794

申请日：2016-08-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sven Beyer ,  Martin Trentzsch ,  Stefan Flachowsky ,  Axel Henke

IPC: H03K3/01 ,  H01L29/51 ,  H01L21/02 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06

CPC classification number: H01L29/516 ,  H01L21/02181 ,  H01L21/02266 ,  H01L21/0228 ,  H01L21/02321 ,  H01L21/823857 ,  H01L21/84 ,  H01L27/1159 ,  H01L27/1203 ,  H01L29/0642 ,  H01L29/40111 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/66628 ,  H01L29/78391 ,  H01L29/78654

Abstract: The present disclosure provides in one aspect a semiconductor device including a substrate structure comprising an active semiconductor material formed over a base substrate and a buried insulating material formed between the active semiconductor material and the base substrate, a ferroelectric gate structure disposed over the active semiconductor material in an active region of the substrate structure, the ferroelectric gate structure comprising a gate electrode and a ferroelectric material layer, and a contact region formed in the base substrate under the ferroelectric gate structure.

公开(公告)号：US20180053832A1

公开(公告)日：2018-02-22

申请号：US15237794

申请日：2016-08-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sven Beyer ,  Martin Trentzsch ,  Stefan Flachowsky ,  Axel Henke

IPC: H01L29/51 ,  H01L27/12 ,  H01L21/84 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L29/516 ,  H01L21/02266 ,  H01L21/0228 ,  H01L21/28185 ,  H01L21/28291 ,  H01L21/84 ,  H01L27/1159 ,  H01L27/1203 ,  H01L29/0642 ,  H01L29/517 ,  H01L29/66628 ,  H01L29/78391 ,  H01L29/786

Abstract: The present disclosure provides in one aspect a semiconductor device including a substrate structure comprising an active semiconductor material formed over a base substrate and a buried insulating material formed between the active semiconductor material and the base substrate, a ferroelectric gate structure disposed over the active semiconductor material in an active region of the substrate structure, the ferroelectric gate structure comprising a gate electrode and a ferroelectric material layer, and a contact region formed in the base substrate under the ferroelectric gate structure.

公开(公告)号：US20180012877A1

公开(公告)日：2018-01-11

申请号：US15713064

申请日：2017-09-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sven Beyer ,  Jan Hoentschel ,  Alexander Ebermann

IPC: H01L25/16 ,  H01L23/00 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L25/167 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/16 ,  H01L24/83 ,  H01L25/043 ,  H01L2224/16146 ,  H01L2224/818 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/12044

Abstract: A method includes forming a stack of semiconductor die. The stack includes a first semiconductor die, a second semiconductor die and a third semiconductor die. The first semiconductor die is stacked above the second semiconductor die and the third semiconductor die is stacked above the first semiconductor die. A first optical transmitter and a first optical receiver are provided in the first semiconductor die, a second optical transmitter is provided in the second semiconductor die, and a second optical receiver is provided in the third semiconductor die. A first optical signal is transmitted from the first optical transmitter in the first semiconductor die to the second optical receiver in the third semiconductor die. A second optical signal is transmitted from the second optical transmitter in the second semiconductor die to the first optical receiver in the first semiconductor die.

公开(公告)号：US09806067B2

公开(公告)日：2017-10-31

申请号：US14803466

申请日：2015-07-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sven Beyer ,  Jan Hoentschel ,  Alexander Ebermann

IPC: H01L25/16 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L25/167 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/16 ,  H01L24/83 ,  H01L25/043 ,  H01L2224/16146 ,  H01L2224/818 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/12044

Abstract: A semiconductor die is provided with an optical transmitter configured to transmit an optical signal to another die and an optical receiver configured to receive an optical signal from another die. Furthermore, a method of forming a semiconductor device is provided including forming a first semiconductor die with the steps of providing a semiconductor substrate, forming a transistor device at least partially over the semiconductor substrate, forming an optical receiver one of at least partially over and at least partially in the semiconductor substrate, forming a metallization layer over the transistor device, and forming an optical transmitter one of at least partially over the metallization layer and at least partially in the metallization layer.

公开(公告)号：US09698179B2

公开(公告)日：2017-07-04

申请号：US15042547

申请日：2016-02-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Sven Beyer ,  Jan Hoentschel ,  Alexander Ebermann

IPC: H01L27/13 ,  H01L49/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L27/13 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1207 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/66477 ,  H01L29/78

Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a capacitor structure comprising an active region formed in a semiconductor substrate, a MOSFET device comprising source and drain regions formed in the active region and a gate electrode formed above the active region, and a first electrode and a second electrode formed in a metallization layer above the MOSFET device, wherein the first electrode is electrically connected with the source and drain regions via respective source and drain contacts and the second electrode is electrically connected with the gate electrode via a gate contact.