公开(公告)号：US20130075913A1

公开(公告)日：2013-03-28

申请号：US13239533

申请日：2011-09-22

申请人： Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Xiao Hu Liu ,  Thomas L. McDevitt ,  Gary L. Milo ,  William J. Murphy

发明人： Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Xiao Hu Liu ,  Thomas L. McDevitt ,  Gary L. Milo ,  William J. Murphy

IPC分类号： H01L23/485 ,  H01L21/3205

CPC分类号： H01L21/76802 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53295 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and a method of fabricating the same, includes vertically stacked layers on an insulator. Each of the layers includes a first dielectric insulator portion, a first metal conductor embedded within the first dielectric insulator portion, a first nitride cap covering the first metal conductor, a second dielectric insulator portion, a second metal conductor embedded within the second dielectric insulator portion, and a second nitride cap covering the second metal conductor. The first and second metal conductors form first vertically stacked conductor layers and second vertically stacked conductor layers. The first vertically stacked conductor layers are proximate the second vertically stacked conductor layers, and at least one air gap is positioned between the first vertically stacked conductor layers and the second vertically stacked conductor layers. An upper semiconductor layer covers the first vertically stacked conductor layers, the air gap and the second plurality of vertically stacked conductor layers.

公开(公告)号：US08368125B2

公开(公告)日：2013-02-05

申请号：US12505580

申请日：2009-07-20

申请人： Dureseti Chidambarrao ,  Xiao Hu Liu ,  Lidija Sekaric

发明人： Dureseti Chidambarrao ,  Xiao Hu Liu ,  Lidija Sekaric

IPC分类号： H01L27/085

CPC分类号： H01L29/775 ,  B82Y10/00 ,  H01L21/823807 ,  H01L21/82385 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7842 ,  H01L29/7845

摘要： An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness tC; and a dielectric film of thickness tg in contact with a surface of the channel. Further, the film comprises a material that exerts one of a compressive or a tensile force on the contacted surface of the channel such that electrical mobility of the charge carriers (electrons or holes) along the channel length is increased due to the compressive or tensile force in dependence on alignment of the channel length relative to the crystal structure. Embodiments are given for chips with both hole and electron mobility increased in different transistors, and a method for making such a transistor or chip.

摘要翻译： 电子器件包括限定晶体结构且具有长度和厚度tC的导电沟道; 以及与沟道的表面接触的厚度为tg的电介质膜。 此外，膜包括在通道的接触表面上施加压缩力或拉力中的一种的材料，使得沿着通道长度的电荷载流子（电子或空穴）的电迁移率由于压缩或拉伸力而增加 取决于通道长度相对于晶体结构的对准。 给出了在不同晶体管中空穴和电子迁移率增加的芯片的实施例，以及制造这种晶体管或芯片的方法。

公开(公告)号：US20120121906A1

公开(公告)日：2012-05-17

申请号：US13356778

申请日：2012-01-24

申请人： Gareth G. Hougham ,  Vijayeshwar D. Khanna ,  Xiao Hu Liu ,  Gerard McVicker

发明人： Gareth G. Hougham ,  Vijayeshwar D. Khanna ,  Xiao Hu Liu ,  Gerard McVicker

IPC分类号： B32B7/04 ,  B32B5/16 ,  B32B7/02

CPC分类号： B32B37/144 ,  B32B38/1866 ,  B32B2311/24 ,  Y10T428/249971 ,  Y10T428/2982

摘要： Methods for the fabrication of negative coefficient thermal expansion engineered elements, and particularly, wherein such elements provide for fillers possessing a low or even potentially zero coefficient thermal expansion and which are employable as fillers for polymers possessing high coefficients of thermal expansion. Further, disclosed are novel structures, which are obtained by the inventive methods.

摘要翻译： 用于制造负系数热膨胀工程元件的方法，特别地，其中这些元件提供具有低或甚至潜在的零系数热膨胀的填料，并且其可用作具有高热膨胀系数的聚合物的填料。 此外，公开了通过本发明方法获得的新颖结构。

公开(公告)号：US08076756B2

公开(公告)日：2011-12-13

申请号：US13031195

申请日：2011-02-19

申请人： Michael W. Lane ,  Xiao Hu Liu ,  Thomas M. Shaw ,  Mukta G. Farooq ,  Robert Hannon ,  Ian D. W. Melville

发明人： Michael W. Lane ,  Xiao Hu Liu ,  Thomas M. Shaw ,  Mukta G. Farooq ,  Robert Hannon ,  Ian D. W. Melville

IPC分类号： H01L23/544

CPC分类号： H01L29/0657 ,  H01L21/563 ,  H01L21/78 ,  H01L23/5329 ,  H01L23/562 ,  H01L23/585 ,  H01L24/90 ,  H01L2224/73203 ,  H01L2224/90 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/18301 ,  H01L2924/00

摘要： A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.

摘要翻译： 半导体产品包括具有顶表面和包括半导体芯片的底表面的半导体衬底。 半导体衬底具有顶表面和周边。 在周边的芯片中形成屏障。 在深度隔离沟槽（UDIT）中切割在芯片的上表面，其在周边和屏障之间向下延伸。 在形成屏障和UDIT之前，在衬底上形成具有低k pSICOH电介质和硬掩模层的ILD结构。 除了UDIT之外，ILD结构互连结构可以向下凹入底层。

公开(公告)号：US07955952B2

公开(公告)日：2011-06-07

申请号：US12174994

申请日：2008-07-17

申请人： Xiao Hu Liu ,  Chih-Chao Yang ,  Haining Sam Yang

发明人： Xiao Hu Liu ,  Chih-Chao Yang ,  Haining Sam Yang

IPC分类号： H01L29/00 ,  H01L21/00

CPC分类号： H01L23/585 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit chip and a method of fabricating an integrated circuit chip. The integrated circuit chip includes: a continuous first stress ring proximate to a perimeter of the integrated circuit chip, respective edges of the first stress ring parallel to respective edges of the integrated circuit chip; a continuous second stress ring between the first stress ring and the perimeter of the integrated circuit chip, respective edges the second stress ring parallel to respective edges of the integrated circuit chip, the first and second stress rings having opposite internal stresses; a continuous gap between the first stress ring and the second stress ring; and a set of wiring levels from a first wiring level to a last wiring level on the substrate.

摘要翻译： 集成电路芯片和制造集成电路芯片的方法。 集成电路芯片包括：接近集成电路芯片的周边的连续的第一应力环，第一应力环的相应边缘平行于集成电路芯片的相应边缘; 所述第一应力环与所述集成电路芯片的周边之间的连续的第二应力环，所述第二应力环平行于所述集成电路芯片的相应边缘的相应边缘，所述第一和第二应力环具有相反的内应力; 第一应力环和第二应力环之间的连续间隙; 以及从基板上的第一布线电平到最后布线电平的一组布线电平。

公开(公告)号：US20090304951A1

公开(公告)日：2009-12-10

申请号：US12542287

申请日：2009-08-17

申请人： Christos Dimitrios Dimitrakopoulos ,  Stephen McConnell Gates ,  Alfred Grill ,  Michael Wayne Lane ,  Eric Gerhard Liniger ,  Xiao Hu Liu ,  Son Van Nguyen ,  Deborah Ann Neumayer ,  Thomas McCarroll Shaw

发明人： Christos Dimitrios Dimitrakopoulos ,  Stephen McConnell Gates ,  Alfred Grill ,  Michael Wayne Lane ,  Eric Gerhard Liniger ,  Xiao Hu Liu ,  Son Van Nguyen ,  Deborah Ann Neumayer ,  Thomas McCarroll Shaw

IPC分类号： C23C16/513 ,  G21G5/00

CPC分类号： H01L21/76834 ,  C23C16/30 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  Y10T428/249953 ,  Y10T428/249969 ,  Y10T428/249979

摘要： A method for forming a ultralow dielectric constant layer with controlled biaxial stress is described incorporating the steps of forming a layer containing Si, C, O and H by one of PECVD and spin-on coating and curing the film in an environment containing very low concentrations of oxygen and water each less than 10 ppm. A material is also described by using the method with a dielectric constant of not more than 2.8. The invention overcomes the problem of forming films with low biaxial stress less than 46 MPa.

摘要翻译： 描述了形成具有受控双轴应力的超低介电常数层的方法，其包括以下步骤：通过PECVD和旋涂方法之一形成包含Si，C，O和H的层，并在含有非常低的浓度的环境中固化该膜 的氧和水各自小于10ppm。 还通过使用介电常数不超过2.8的方法描述材料。 本发明克服了低双轴应力低于46MPa的薄膜形成问题。

公开(公告)号：US20090169886A1

公开(公告)日：2009-07-02

申请号：US11967459

申请日：2007-12-31

申请人： Gareth G. Hougham ,  Vijayeshwar D. Khanna ,  Xiao Hu Liu ,  Gerard McVicker

发明人： Gareth G. Hougham ,  Vijayeshwar D. Khanna ,  Xiao Hu Liu ,  Gerard McVicker

IPC分类号： B32B5/16 ,  B23K26/20

CPC分类号： B32B37/144 ,  B32B38/1866 ,  B32B2311/24 ,  Y10T428/249971 ,  Y10T428/2982

摘要： Methods for the fabrication of negative coefficient thermal expansion engineered elements, and particularly, wherein such elements provide for fillers possessing a low or even potentially zero coefficient thermal expansion and which are employable as fillers for polymers possessing high coefficients of thermal expansion. Further, disclosed are novel structures, which are obtained by the inventive methods.

摘要翻译： 用于制造负系数热膨胀工程元件的方法，特别地，其中这些元件提供具有低或甚至潜在的零系数热膨胀的填料，并且其可用作具有高热膨胀系数的聚合物的填料。 此外，公开了通过本发明方法获得的新颖结构。

公开(公告)号：US07491965B2

公开(公告)日：2009-02-17

申请号：US12127994

申请日：2008-05-28

申请人： James P. Doyle ,  Bruce G. Elmegreen ,  Lia Krusin-Elbaum ,  Chung Hon Lam ,  Xiao Hu Liu ,  Dennis M. Newns ,  Christy S. Tyberg

发明人： James P. Doyle ,  Bruce G. Elmegreen ,  Lia Krusin-Elbaum ,  Chung Hon Lam ,  Xiao Hu Liu ,  Dennis M. Newns ,  Christy S. Tyberg

IPC分类号： H01L47/00

CPC分类号： H01L45/1233 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1286 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1666

摘要： An electrically re-programmable fuse (eFUSE) device for use in integrated circuit devices includes an elongated heater element, an electrically insulating liner surrounding an outer surface of the elongated heater element, corresponding to a longitudinal axis thereof, leaving opposing ends of the elongated heater element in electrical contact with first and second heater electrodes. A phase change material (PCM) surrounds a portion of an outer surface of the electrically insulating liner, a thermally and electrically insulating layer surrounds an outer surface of the PCM, with first and second fuse electrodes in electrical contact with opposing ends of the PCM. The PCM is encapsulated within the electrically insulating liner, the thermally and electrically insulating layer, and the first and second fuse electrodes.

摘要翻译： 用于集成电路器件的电可重新编程保险丝（eFUSE）器件包括细长的加热器元件，围绕细长加热器元件的外表面的电绝缘衬垫，其对应于其纵向轴线，留下细长加热器的相对端 元件与第一和第二加热器电极电接触。 相变材料（PCM）围绕电绝缘衬垫的外表面的一部分，热和电绝缘层围绕PCM的外表面，其中第一和第二熔丝电极与PCM的相对端电接触。 PCM被封装在电绝缘衬垫，热和电绝缘层以及第一和第二熔丝电极中。

公开(公告)号：US07357977B2

公开(公告)日：2008-04-15

申请号：US11034479

申请日：2005-01-13

申请人： Christos Dimitrios Dimitrakopoulos ,  Stephen McConnell Gates ,  Alfred Grill ,  Michael Wayne Lane ,  Eric Gerhard Liniger ,  Xiao Hu Liu ,  Son Van Nguyen ,  Deborah Ann Neumayer ,  Thomas McCarroll Shaw

发明人： Christos Dimitrios Dimitrakopoulos ,  Stephen McConnell Gates ,  Alfred Grill ,  Michael Wayne Lane ,  Eric Gerhard Liniger ,  Xiao Hu Liu ,  Son Van Nguyen ,  Deborah Ann Neumayer ,  Thomas McCarroll Shaw

IPC分类号： H01L23/52 ,  H01L23/58

CPC分类号： H01L21/76834 ,  C23C16/30 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  Y10T428/249953 ,  Y10T428/249969 ,  Y10T428/249979

摘要： A method for forming a ultralow dielectric constant layer with controlled biaxial stress is described incorporating the steps of forming a layer containing Si, C, O and H by one of PECVD and spin-on coating and curing the film in an environment containing very low concentrations of oxygen and water each less than 10 ppm. A material is also described by using the method with a dielectric constant of not more than 2.8. The invention overcomes the problem of forming films with low biaxial stress less than 46 MPa.

摘要翻译： 描述了形成具有受控双轴应力的超低介电常数层的方法，其包括以下步骤：通过PECVD和旋涂方法之一形成包含Si，C，O和H的层，并在含有非常低的浓度的环境中固化该膜 的氧和水各自小于10ppm。 还通过使用介电常数不大于2.8的方法描述材料。 本发明克服了低双轴应力低于46MPa的薄膜形成问题。

公开(公告)号：US20080048169A1

公开(公告)日：2008-02-28

申请号：US11467294

申请日：2006-08-25

申请人： James P. Doyle ,  Bruce G. Elmegreen ,  Lia Krusin-Elbaum ,  Chung Hon Lam ,  Xiao Hu Liu ,  Dennis M. Newns ,  Christy S. Tyberg

发明人： James P. Doyle ,  Bruce G. Elmegreen ,  Lia Krusin-Elbaum ,  Chung Hon Lam ,  Xiao Hu Liu ,  Dennis M. Newns ,  Christy S. Tyberg

IPC分类号： H01L47/00 ,  H01L21/76

CPC分类号： H01L45/1233 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1286 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1666

摘要： An electrically re-programmable fuse (eFUSE) device for use in integrated circuit devices includes an elongated heater element, an electrically insulating liner surrounding an outer surface of the elongated heater element, corresponding to a longitudinal axis thereof, leaving opposing ends of the elongated heater element in electrical contact with first and second heater electrodes. A phase change material (PCM) surrounds a portion of an outer surface of the electrically insulating liner, a thermally and electrically insulating layer surrounds an outer surface of the PCM, with first and second fuse electrodes in electrical contact with opposing ends of the PCM. The PCM is encapsulated within the electrically insulating liner, the thermally and electrically insulating layer, and the first and second fuse electrodes.

摘要翻译： 用于集成电路器件的电可重新编程保险丝（eFUSE）器件包括细长的加热器元件，围绕细长加热器元件的外表面的电绝缘衬垫，其对应于其纵向轴线，留下细长加热器的相对端 元件与第一和第二加热器电极电接触。 相变材料（PCM）围绕电绝缘衬垫的外表面的一部分，热和电绝缘层围绕PCM的外表面，其中第一和第二熔丝电极与PCM的相对端电接触。 PCM被封装在电绝缘衬垫，热和电绝缘层以及第一和第二熔丝电极中。