公开(公告)号：US10217900B2

公开(公告)日：2019-02-26

申请号：US15643061

申请日：2017-07-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Deepak K. Nayak ,  Srinivasa R. Banna ,  Ajey P. Jacob

IPC: H01L33/12 ,  H01L33/00 ,  H01L33/06 ,  H01L33/32 ,  H01L33/22

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to light emitting diode (LED) structures and methods of manufacture. The method includes: forming a buffer layer on a substrate, the buffer layer having at least a lattice mismatch with the substrate; and relaxing the buffer layer by pixelating the buffer layer into discrete islands, prior to formation of a quantum well.

公开(公告)号：US09953882B2

公开(公告)日：2018-04-24

申请号：US15792281

申请日：2017-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey P. Jacob

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/786 ,  H01L29/423 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: Methods for forming a NW with multiple devices having alternate channel materials and resulting devices are disclosed. Embodiments include forming a first stack of semiconductor layers including a first doped Si layer, a first channel layer, and a second doped Si layer, respectively, on a Si substrate; forming a second stack including a first doped SiGe layer, a second channel layer, and a second doped SiGe layer, respectively, on the first stack; forming a vertical nanowire structure by directional etching, along a three-dimensional plane, the second and first stacks, respectively, down to an upper surface of the Si substrate; forming lower S/D regions and a lower gate-stack surrounding the first stack; forming upper S/D regions and an upper gate-stack surrounding the second stack; and forming contacts to the lower S/D regions, a first gate electrode, an upper S/D region, an upper gate electrode, and the second doped SiGe layer.

公开(公告)号：US09385233B2

公开(公告)日：2016-07-05

申请号：US13927698

申请日：2013-06-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat K. Akarvardar ,  Ajey P. Jacob

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/1083 ,  H01L21/02236 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/76216 ,  H01L21/76281 ,  H01L27/0255 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A bulk finFET with partial dielectric isolation is disclosed. The dielectric isolation is disposed underneath the channel, and essentially bounded by the channel, such that it does not extend laterally beyond the channel under the source and drain regions. This allows increased volume of SiGe source and drain stressor regions placed adjacent to the channel, allowing for a more strained channel, which improves carrier mobility. An N+ doped silicon region is disposed below the dielectric isolation and extends laterally beyond the channel and underneath the stressor source and drain regions, forming a reverse-biased p/n junction with the P+ doped source and drain SiGe stressor to minimize leakage currents from under the insulator.

Abstract translation: 公开了具有部分电介质隔离的散装finFET。 电介质隔离设置在通道下方，并且基本上由通道限定，使得其不横向延伸超过源极和漏极区下方的沟道。 这允许增加与沟道相邻放置的SiGe源极和漏极应力器体积，从而允许更加紧张的通道，这改善了载流子迁移率。 N +掺杂的硅区域设置在电介质隔离的下方，并横向延伸超过沟道并且在应力源和漏极区之下，与P +掺杂的源极和漏极SiGe应力器形成反向偏置的p / n结，以使来自下面的漏电流最小化 绝缘体。

公开(公告)号：US09293324B2

公开(公告)日：2016-03-22

申请号：US14274406

申请日：2014-05-09

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Steven Bentley ,  Ajey P. Jacob

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L21/02538 ,  H01L29/20 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices including a fin and method of forming the semiconductor devices are provided herein. In an embodiment, a method of forming a semiconductor device includes forming a fin overlying a semiconductor substrate. The fin is formed by epitaxially-growing a semiconductor material over the semiconductor substrate, and the fin has a first portion that is proximal to the semiconductor substrate and a second portion that is spaced from the semiconductor substrate by the first portion. A gate structure is formed over the fin and the semiconductor substrate. The first portion of the fin is etched to form a gap between the second portion and the semiconductor substrate.

Abstract translation: 本文提供了包括翅片的半导体器件和形成半导体器件的方法。 在一个实施例中，形成半导体器件的方法包括形成覆盖半导体衬底的散热片。 鳍状物通过在半导体衬底上外延生长半导体材料而形成，并且鳍具有靠近半导体衬底的第一部分和通过第一部分与半导体衬底间隔开的第二部分。 在鳍片和半导体衬底上形成栅极结构。 蚀刻鳍的第一部分以在第二部分和半导体衬底之间形成间隙。

公开(公告)号：US20160071979A1

公开(公告)日：2016-03-10

申请号：US14476830

申请日：2014-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey P. Jacob ,  Min-Hwa Chi

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L21/311 ,  H01L29/16 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L29/0638 ,  H01L21/02164 ,  H01L21/02255 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method includes forming an ion implant layer in a fin defined on a semiconductor substrate. The semiconductor substrate is annealed to convert the ion implant layer to a dielectric layer. A gate electrode structure is formed above the fin in a channel region after forming the ion implant layer. The fin is recessed in a source/drain region. A semiconductor material is epitaxially grown in the source/drain region.

Abstract translation: 一种方法包括在限定在半导体衬底上的翅片上形成离子注入层。 将半导体衬底退火以将离子注入层转换成电介质层。 在形成离子注入层之后的沟道区域中，在鳍的上方形成栅电极结构。 鳍片凹陷在源极/漏极区域中。 在源极/漏极区域中外延生长半导体材料。

公开(公告)号：US20160064250A1

公开(公告)日：2016-03-03

申请号：US14931277

申请日：2015-11-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey P. Jacob ,  Murat K. Akarvardar ,  Jody Fronheiser ,  Witold P. Maszara

IPC: H01L21/3205 ,  H01L21/3105

CPC classification number: H01L21/32055 ,  H01L21/3105 ,  H01L21/76224 ,  H01L27/1203 ,  H01L29/66628 ,  H01L29/66765 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Various methods are disclosed herein for forming alternative fin materials that are in a stable or metastable condition. In one case, a metastable replacement fin is grown to a height that is greater than an unconfined stable critical thickness of the replacement fin material and it has a defect density of 105 defects/cm2 or less throughout at least 90% of its entire height. In another case, a metastable replacement fin is grown to a height that is greater than an unconfined metastable critical thickness of the replacement fin material and it has a defect density of 105 defects/cm2 or less throughout at least 90% of its entire height.

Abstract translation: 本文公开了用于形成处于稳定或亚稳态的替代翅片材料的各种方法。 在一种情况下，亚稳态替代翅片生长到大于置换翅片材料的无约束稳定的临界厚度的高度，并且在其整个高度的至少90％中具有105缺陷/ cm2或更小的缺陷密度。 在另一种情况下，亚稳替代鳍生长到高于替代翅片材料的无约束亚稳临界厚度的高度，并且在其整个高度的至少90％中具有105缺陷/ cm2或更小的缺陷密度。

公开(公告)号：US20150024573A1

公开(公告)日：2015-01-22

申请号：US13944200

申请日：2013-07-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey P. Jacob ,  Murat K. Akarvardar ,  Jody Fronheiser ,  Witold P. Maszara

IPC: H01L21/762

CPC classification number: H01L21/32055 ,  H01L21/3105 ,  H01L21/76224 ,  H01L27/1203 ,  H01L29/66628 ,  H01L29/66765 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Various methods are disclosed herein for forming alternative fin materials that are in a stable or metastable condition. In one case, a stable replacement fin is grown to a height that is greater than an unconfined stable critical thickness of the replacement fin material and it has a defect density of 104 defects/cm2 or less throughout its entire height. In another case, a metastable replacement fin is grown to a height that is greater than an unconfined metastable critical thickness of the replacement fin material and it has a defect density of 105 defects/cm2 or less throughout at least 90% of its entire height.

Abstract translation: 本文公开了用于形成处于稳定或亚稳态的替代翅片材料的各种方法。 在一种情况下，稳定的替换翅片生长到比替换翅片材料的无约束的稳定的临界厚度大的高度，并且其整个高度的缺陷密度为104个缺陷/ cm2或更小。 在另一种情况下，亚稳替代鳍生长到高于替代翅片材料的无约束亚稳临界厚度的高度，并且在其整个高度的至少90％中具有105缺陷/ cm2或更小的缺陷密度。

公开(公告)号：US20150001591A1

公开(公告)日：2015-01-01

申请号：US13927698

申请日：2013-06-26

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Murat K. Akarvardar ,  Ajey P. Jacob

IPC: H01L29/78 ,  H01L21/265

CPC classification number: H01L29/1083 ,  H01L21/02236 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/76216 ,  H01L21/76281 ,  H01L27/0255 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A bulk finFET with partial dielectric isolation is disclosed. The dielectric isolation is disposed underneath the channel, and essentially bounded by the channel, such that it does not extend laterally beyond the channel under the source and drain regions. This allows increased volume of SiGe source and drain stressor regions placed adjacent to the channel, allowing for a more strained channel, which improves carrier mobility. An N+ doped silicon region is disposed below the dielectric isolation and extends laterally beyond the channel and underneath the stressor source and drain regions, forming a reverse-biased p/n junction with the P+ doped source and drain SiGe stressor to minimize leakage currents from under the insulator.

Abstract translation: 公开了具有部分电介质隔离的散装finFET。 电介质隔离设置在通道下方，并且基本上由通道限定，使得其不横向延伸超过源极和漏极区下方的沟道。 这允许增加与沟道相邻放置的SiGe源极和漏极应力器体积，从而允许更加紧张的通道，这改善了载流子迁移率。 N +掺杂的硅区域设置在电介质隔离的下方，并横向延伸超过沟道并且在应力源和漏极区之下，与P +掺杂的源极和漏极SiGe应力器形成反向偏置的p / n结，以使来自下面的漏电流最小化 绝缘体。

公开(公告)号：US20200098976A1

公开(公告)日：2020-03-26

申请号：US16142432

申请日：2018-09-26

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ajey P. Jacob ,  Eswar Ramanathan

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: Integrated circuits with embedded memory structures, and methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes forming first and second conductive interconnects over a semiconductor substrate. The method includes depositing a conductive material over the first conductive interconnect. Also, the method includes forming a memory structure over the conductive material, wherein the memory structure has an uppermost surface distanced from the first conductive interconnect by a first height. Further, the method includes forming an interlayer dielectric over the memory structure and forming a conductive via coupled to the second conductive interconnect, wherein the conductive via has a second height over the second conductive interconnect less than the first height. The method also includes forming first and second contact plugs through the interlayer dielectric. The first contact plug contacts the memory structure and the second contact plug contacts the conductive via.

公开(公告)号：US10396121B2

公开(公告)日：2019-08-27

申请号：US15680948

申请日：2017-08-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey P. Jacob ,  Srinivasa Banna ,  Deepak Nayak

IPC: H01L27/15 ,  H01L33/06 ,  H01L33/24 ,  H01L33/00 ,  H01L33/32 ,  H01L33/60 ,  H01L33/50 ,  H01L29/78

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs for light emitting diode displays and methods of manufacture. The method includes: forming replacement fin structures with a doped core region, on doped substrate material; forming quantum wells over the replacement fin structures; forming a first color emitting region by doping at least one of the quantum wells over at least a first replacement fin structure of the replacement fin structures, while protecting at least a second replacement fin structure of the replacement fin structures; and forming a second color emitting region by doping another one of the quantum wells over the at least second replacement fin structure of the replacement fin structures, while protecting the first replacement fin structure and other replacement fin structures which are not to be doped.