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    Metallization Process for an Integrated Circuit
    11.
    发明公开
    Metallization Process for an Integrated Circuit 审中-公开

    公开(公告)号：US20230197514A1

    公开(公告)日：2023-06-22

    申请号：US18066400

    申请日：2022-12-15

    Applicant: IMEC VZW

    Inventor： Victor Hugo Vega Gonzalez ,  Bilal Chehab ,  Julien Ryckaert ,  Zsolt Tokei ,  Serge Biesemans ,  Naoto Horiguchi

    IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/522

    CPC classification number: H01L21/76897 ,  H01L21/32139 ,  H01L21/76885 ,  H01L23/5226 ,  H01L21/32136 ,  H01L27/092

    Abstract: The disclosure relates to a metallization process for an integrated circuit. One example metallization process includes a method for forming an integrated circuit that includes providing a semiconductor structure having two transistor structures, a gate structure, electrically conductive contacts, a first electrically conductive line, a first electrically conductive via, a second electrically conductive via. The method further includes providing a planar dielectric material in contact with the first electrically conductive line, forming an opening in the planar dielectric material, filling the opening with a planar electrically conductive material, forming an electrically conductive layer arranged within a second metallization level, the electrically conductive layer being in physical contact with the planar dielectric material and in physical and electrical contact with the electrically conductive material, providing a hard mask comprising a set of parallel lines, and etching the electrically conductive layer and the planar electrically conductive material by using the hard mask lines as a mask.

    Self-aligned contacts for nanosheet field effect transistor devices
    12.
    发明授权
    Self-aligned contacts for nanosheet field effect transistor devices 有权

    公开(公告)号：US11462443B2

    公开(公告)日：2022-10-04

    申请号：US17110604

    申请日：2020-12-03

    Applicant: IMEC vzw

    Inventor： Eugenio Dentoni Litta ,  Juergen Boemmels ,  Julien Ryckaert ,  Naoto Horiguchi ,  Pieter Weckx

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66

    Abstract: In one aspect, a method of forming a semiconductor device, can comprise forming a first transistor structure and a second transistor structure separated by a trench. The first and the second transistor structures can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. A first and a second spacer can beformed in the trench at sidewalls of the transistor structures, both protruding above a top surface of the transistor structures. The method can comprise applying a first mask layer including an opening exposing the first spacer at a first source/drain portion of the first transistor structure and covering the second spacer, partially etching the exposed first spacer through the opening, exposing at least parts of a sidewall of the first source/drain portion of the first transistor structure, and removing the mask layer. The method can further comprise depositing a contact material over the transistor structures and the first and second spacer, filling the trench and contacting the first source/drain portion of the first transistor structure, and etching back the contact material layer below a top surface of the second spacer.

    Method for Forming a Buried Metal Line
    13.
    发明申请
    Method for Forming a Buried Metal Line 有权

    公开(公告)号：US20210035860A1

    公开(公告)日：2021-02-04

    申请号：US16945858

    申请日：2020-08-01

    Applicant: IMEC VZW

    Inventor： Eugenio Dentoni Litta ,  Anshul Gupta ,  Julien Ryckaert ,  Boon Teik Chan

    IPC: H01L21/768 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/8234

    Abstract: A method for forming a buried metal line in a substrate includes forming, at a position between a pair of semiconductor structures protruding from the substrate, a metal line trench in the substrate at a level below a base of each semiconductor structure of the pair. Forming the metal line trench includes etching an upper trench portion in the substrate, forming a spacer on sidewall surfaces of the upper trench portion that expose a bottom surface of the upper trench portion, and, while the spacer masks the sidewall surfaces, etching a lower trench portion by etching the substrate via the upper trench portion such that a width of the lower trench portion exceeds a width of the upper trench portion. The method further includes forming the metal line in the metal line trench.

    METHOD OF FORMING VERTICAL TRANSISTOR DEVICE
    16.
    发明申请
    METHOD OF FORMING VERTICAL TRANSISTOR DEVICE 审中-公开

    公开(公告)号：US20180330997A1

    公开(公告)日：2018-11-15

    申请号：US15977381

    申请日：2018-05-11

    Applicant: IMEC VZW ,  Vrije Universiteit Brussel

    Inventor： Julien Ryckaert ,  Naoto Horiguchi ,  Dan Mocuta ,  Trong Huynh Bao

    IPC: H01L21/8238 ,  H01L21/285 ,  H01L21/306 ,  H01L21/308 ,  H01L21/762 ,  H01L23/528 ,  H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L29/45 ,  H01L29/78

    Abstract: The disclosed technology generally relates to semiconductor fabrication and more particularly to forming vertical transistor devices. In an aspect, a method of forming a vertical transistor device includes forming, on a substrate, a fin comprising a stack including a first layer, a second layer formed above the first layer and a third layer formed above the second layer. The method additionally includes forming a gate layer serving as an etch mask above the third layer. The method further includes etching the second and third layers of the fin using the gate layer as the etch mask to form a pillar. First and third layers of the pillar define a source region and a drain region, respectively, of the vertical transistor device. A second layer of the pillar defines a channel region of the vertical transistor device. The gate layer comprises a gate electrode arranged on at least one sidewall of the second layer.

    STANDARD CELL HAVING VERTICAL TRANSISTORS
    17.
    发明申请
    STANDARD CELL HAVING VERTICAL TRANSISTORS 审中-公开

    公开(公告)号：US20180190670A1

    公开(公告)日：2018-07-05

    申请号：US15858821

    申请日：2017-12-29

    Applicant: IMEC VZW ,  VRIJE UNIVERSITEIT BRUSSEL

    Inventor： Julien Ryckaert ,  Trong Huynh Bao

    IPC: H01L27/118 ,  H01L27/02

    CPC classification number: H01L27/11807 ,  B82Y10/00 ,  H01L27/0207 ,  H01L29/0676 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/78642 ,  H01L2027/11816 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2027/11881

    Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to a standard cell semiconductor device comprising transistors having vertical channels and a common gate. In one aspect, a standard cell semiconductor device comprises a substrate, a unit cell having a first transistor and a second transistor, a gate layer common to the first and second transistor, and a set of routing tracks for contacting the first and second transistor. Each one of the first and second transistors is formed of a stack of layers arranged between at least some of the routing tracks and the substrate, wherein each stack comprises a bottom terminal arranged on the substrate, a channel arranged on the bottom terminal and a top terminal arranged on the channel. The channel of the first transistor is an N-type channel, and the channel of the second transistor is a P-type channel. Further, the routing tracks comprises a pair of power routing tracks arranged on opposite sides of the unit cell and adapted to contact the top terminal of the first and second transistors, and a gate track arranged between the pair of power routing tracks and adapted to contact the gate layer at a position beside the unit cell.

    Method for Forming a Semiconductor Device
    18.
    发明公开
    Method for Forming a Semiconductor Device 审中-公开

    公开(公告)号：US20240204082A1

    公开(公告)日：2024-06-20

    申请号：US18543933

    申请日：2023-12-18

    Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

    Inventor： Boon Teik Chan ,  Shairfe Muhammad Salahuddin ,  Julien Ryckaert ,  Bilal Chehab ,  Hsiao-Hsuan Liu

    IPC: H01L29/66 ,  H01L21/306

    CPC classification number: H01L29/66545 ,  H01L21/306 ,  H01L29/66439

    Abstract: Example embodiments relate to methods for forming a semiconductor device. One example method includes forming a device structure on a substrate, where the device structure includes a device layer stack that includes a bottom device sub-stack that includes at least one bottom channel layer and a top device sub-stack that includes at least one top channel layer, a sacrificial gate structure extending across the device layer stack, and bottom source/drain structures on opposite ends of at least one bottom channel layer. The method also includes forming an opening exposing the top device sub-stack, wherein forming the opening includes etching the sacrificial gate structure, forming a cut through the top device sub-stack by etching back the top device sub-stack from the opening and, subsequent to forming the cut, forming a functional gate stack on the at least one bottom channel layer.

    3D integrated count
    19.
    发明授权
    3D integrated count 有权

    公开(公告)号：US11677401B2

    公开(公告)日：2023-06-13

    申请号：US17740759

    申请日：2022-05-10

    Applicant: IMEC VZW

    Inventor： Francky Catthoor ,  Edouard Giacomin ,  Juergen Boemmels ,  Julien Ryckaert

    IPC: H03K19/17736 ,  H01L27/06

    CPC classification number: H03K19/17744 ,  H01L27/0688

    Abstract: According to an aspect of the present inventive concept there is provided 3D IC, comprising:



    a plurality of logic cells stacked on top of each other, each logic cell forming part of one of a plurality of vertically stacked device tiers of the 3D IC, and each logic cell comprising a network of logic gates, each logic gate comprising a network of horizontal channel transistors,
    wherein a layout of the network of logic gates of each logic cell is identical among said logic cells such that each logic gate of any one of said logic cells has a corresponding logic gate in each other one of said logic cells, and
    wherein each logic cell comprises:

    a single active layer forming an active semiconductor pattern of the transistors of the logic gates of the logic cell, and
    a single layer of horizontally extending conductive lines comprising gate lines defining transistor gates of the transistors, and wiring lines forming interconnections in the network of transistors and in the network of logic gates of said logic cell.

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