公开(公告)号：US09647029B2

公开(公告)日：2017-05-09

申请号：US14979533

申请日：2015-12-28

Applicant: Industrial Technology Research Institute

Inventor： Wei-Chung Lo ,  Yu-Wei Huang ,  Tao-Chih Chang ,  Chih-Ming Shen

IPC: H01L21/00 ,  H01L27/15 ,  H01L33/38 ,  H01L33/00 ,  H01L33/62

CPC classification number: H01L27/156 ,  H01L25/0753 ,  H01L33/005 ,  H01L33/38 ,  H01L33/62 ,  H01L2224/48139 ,  H01L2933/0016 ,  H01L2933/0066

Abstract: In an embodiment, a light emitting device comprises a light emitting diode chip and a spherical extending electrode. The light emitting diode chip includes a semiconductor epitaxial structure, a first electrode and a second electrode. The first electrode and the second electrode are disposed on two opposite sides of the semiconductor epitaxial structure, respectively. The first electrode is disposed between the semiconductor epitaxial structure and the spherical extending electrode, and the spherical extending electrode is electrically connected to the semiconductor epitaxial structure electrically through the first electrode. The volume of the spherical extending electrode is greater than that of the light emitting diode chip.

公开(公告)号：US20210082810A1

公开(公告)日：2021-03-18

申请号：US17095744

申请日：2020-11-12

Applicant: Industrial Technology Research Institute ,  Unimicron Technology Corp.

Inventor： Yu-Hua Chen ,  Wei-Chung Lo ,  Tao-Chih Chang ,  Yu-Min Lin ,  Sheng-Tsai Wu

IPC: H01L23/522 ,  H01L23/498 ,  H01L21/48 ,  H01L25/04

Abstract: A package substrate includes a substrate, an insulating protective layer and an interposer. The substrate has a first surface and a second surface opposing to the first surface. The substrate includes a plurality of first conductive pads embedded in the first surface. The insulating protective layer is disposed on the first surface of the substrate. The insulating protective layer has an opening for exposing the first conductive pads embedded in the first surface of the substrate. The interposer has a top surface and a bottom surface opposing to the top surface. The interposer includes a plurality of conductive vias and a plurality of second conductive pads located on the bottom surface. The interposer is located in a recess defined by the opening of the insulating protective layer and the first surface of the substrate. Each of the second conductive pads is electrically connected to corresponding first conductive pad.

公开(公告)号：US10276908B2

公开(公告)日：2019-04-30

申请号：US15468796

申请日：2017-03-24

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Yu-Wei Huang ,  Shih-Hsien Wu ,  Wei-Chung Lo

IPC: H01P3/12

Abstract: An electromagnetic wave transmission board comprises a substrate. The substrate comprises a first dielectric layer and a second dielectric layer, and the first dielectric layer is stacked on the second dielectric layer. The first dielectric layer and the second dielectric layer together form a wave guiding space. The wave guiding space is configured for transmitting electromagnetic wave.

公开(公告)号：US20180323143A1

公开(公告)日：2018-11-08

申请号：US16036946

申请日：2018-07-17

Applicant: Industrial Technology Research Institute ,  Unimicron Technology Corp.

Inventor： Yu-Hua Chen ,  Wei-Chung Lo ,  Dyi-Chung Hu ,  Chang-Hong Hsieh

IPC: H01L23/522 ,  H01L25/04 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/5226 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L25/04 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A package substrate and a method of fabricating the package substrate are provided. The package substrate includes a substrate having a first surface including a plurality of conductive pads and a second surface; an insulating protective layer formed on the first surface of the substrate; an interposer embedded in and exposed from the insulating protective layer; and at least a passive component provided on the first surface of the substrate. The insulating protective layer includes at least an opening for exposing at least one of the conductive pads, and the at least the passive component is directly provided on the conductive pad exposed from the opening.

公开(公告)号：US20170104027A1

公开(公告)日：2017-04-13

申请号：US14979533

申请日：2015-12-28

Applicant: Industrial Technology Research Institute

Inventor： Wei-Chung Lo ,  Yu-Wei Huang ,  Tao-Chih Chang ,  Chih-Ming Shen

IPC: H01L27/15 ,  H01L33/00 ,  H01L33/62 ,  H01L33/38

CPC classification number: H01L27/156 ,  H01L25/0753 ,  H01L33/005 ,  H01L33/38 ,  H01L33/62 ,  H01L2224/48139 ,  H01L2933/0016 ,  H01L2933/0066

Abstract: In an embodiment, a light emitting device comprises a light emitting diode chip and a spherical extending electrode. The light emitting diode chip includes a semiconductor epitaxial structure, a first electrode and a second electrode. The first electrode and the second electrode are disposed on two opposite sides of the semiconductor epitaxial structure, respectively. The first electrode is disposed between the semiconductor epitaxial structure and the spherical extending electrode, and the spherical extending electrode is electrically connected to the semiconductor epitaxial structure electrically through the first electrode. The volume of the spherical extending electrode is greater than that of the light emitting diode chip.

公开(公告)号：US09252054B2

公开(公告)日：2016-02-02

申请号：US14484970

申请日：2014-09-12

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Sheng-Tsai Wu ,  Heng-Chieh Chien ,  John H. Lau ,  Yu-Lin Chao ,  Wei-Chung Lo

IPC: H01L23/367 ,  H01L21/768 ,  H01L21/48 ,  H01L23/42 ,  H01L23/427 ,  H01L23/433 ,  H01L21/50 ,  H01L21/56 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L25/18

CPC classification number: H01L21/76898 ,  H01L21/4882 ,  H01L21/50 ,  H01L21/563 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/4275 ,  H01L23/433 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16235 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/16153 ,  H01L2924/16251 ,  H01L2924/1659 ,  H01L2924/167 ,  H01L2924/16724 ,  H01L2924/16747 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: A thinned integrated circuit device and manufacturing process for the same are disclosed. The manufacturing process includes forming a through-silicon via (TSV) on a substrate, a first terminal of the TSV is exposed on a first surface of the substrate, disposing a bump on the first surface of the substrate to make the bump electrically connected with the TSV, disposing an integrated circuit chip (IC) on the bump so that a first side of the IC is connected to the bump, disposing a thermal interface material (TIM) layer on a second side of the IC opposite to the first side of the IC, attaching a heat-spreader cap on the IC by the TIM layer, and backgrinding a second surface of the substrate to expose the TSV to the second surface of the substrate while carrying the heat-spreader cap.

Abstract translation: 公开了一种薄型集成电路器件及其制造方法。 制造工艺包括在衬底上形成贯通硅通孔（TSV），将TSV的第一端子暴露在衬底的第一表面上，在衬底的第一表面上设置凸块以使凸块电连接到 所述TSV在所述突起上设置集成电路芯片（IC），使得所述IC的第一侧连接到所述凸块，在所述IC的第二侧的第二侧上设置热界面材料（TIM）层， IC，通过TIM层将散热器帽附接到IC上，并且背衬研磨衬底的第二表面以在承载散热器盖的同时将TSV暴露于衬底的第二表面。

公开(公告)号：US09111774B2

公开(公告)日：2015-08-18

申请号：US13774939

申请日：2013-02-22

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Chi-Shih Chang ,  Ra-Min Tain ,  Shyi-Ching Liau ,  Wei-Chung Lo ,  Rong-Shen Lee

IPC: H01L29/40 ,  H01L25/065 ,  H01L23/498 ,  H01L23/48 ,  H01L23/00 ,  H01L23/552 ,  H01L23/60 ,  H01L23/64

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/552 ,  H01L23/562 ,  H01L23/60 ,  H01L23/642 ,  H01L24/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00

Abstract: A wafer stack includes: a first wafer having a first substrate and a first device layer having therein at least a chip; a second wafer having a second substrate disposed above the first wafer; and at least a first metal post existing in the first device layer, and arranged between the first and the second substrates, without being electrically connected to the chip.

Abstract translation: 晶片堆叠包括：第一晶片，具有第一基板和至少在其中具有芯片的第一器件层; 具有设置在所述第一晶片上方的第二基板的第二晶片; 以及至少第一金属柱，其存在于所述第一器件层中，并且布置在所述第一和第二基板之间，而不与所述芯片电连接。