公开(公告)号：US11641779B2

公开(公告)日：2023-05-02

申请号：US17208495

申请日：2021-03-22

Applicant: Infineon Technologies AG

Inventor： Christian Kasztelan ,  Alexander Breymesser ,  Manfred Mengel ,  Andreas Niederhofer

IPC: H01L35/34 ,  H01L35/32 ,  H01L35/22 ,  H01L35/16

Abstract: A method includes forming a plurality of first semiconductor mesa structures at a first semiconductor substrate. The first semiconductor substrate has a first conductivity type. The method further includes forming a plurality of second semiconductor mesa structures at a second semiconductor substrate. The second semiconductor substrate has a second conductivity type. The method further includes providing a glass substrate between the first semiconductor substrate and the second semiconductor substrate. The method includes connecting the first semiconductor substrate to the second semiconductor substrate so that at least a portion of the glass substrate is located laterally between the first semiconductor mesa structures of the plurality of first semiconductor mesa structures and the second semiconductor mesa structures of the plurality of second semiconductor mesa structures.

公开(公告)号：US20210210669A1

公开(公告)日：2021-07-08

申请号：US17208495

申请日：2021-03-22

Applicant: Infineon Technologies AG

Inventor： Christian Kasztelan ,  Alexander Breymesser ,  Manfred Mengel ,  Andreas Niederhofer

IPC: H01L35/32 ,  H01L35/34 ,  H01L35/22 ,  H01L35/16

Abstract: A method includes forming a plurality of first semiconductor mesa structures at a first semiconductor substrate. The first semiconductor substrate has a first conductivity type. The method further includes forming a plurality of second semiconductor mesa structures at a second semiconductor substrate. The second semiconductor substrate has a second conductivity type. The method further includes providing a glass substrate between the first semiconductor substrate and the second semiconductor substrate. The method includes connecting the first semiconductor substrate to the second semiconductor substrate so that at least a portion of the glass substrate is located laterally between the first semiconductor mesa structures of the plurality of first semiconductor mesa structures and the second semiconductor mesa structures of the plurality of second semiconductor mesa structures.

公开(公告)号：US11049790B2

公开(公告)日：2021-06-29

申请号：US15256640

申请日：2016-09-05

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Manfred Mengel

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/433 ,  H01L21/52 ,  H01L21/56 ,  H01L21/3105 ,  H01L21/48 ,  H01L23/495 ,  H01L23/00 ,  H01L23/373

Abstract: Method for manufacturing an electronic semiconductor package, in which method an electronic chip (100) is coupled to a carrier, the electronic chip is at least partially encapsulated by means of an encapsulation structure having a discontinuity, and the carrier is partially encapsulated, and at least one part of the discontinuity and a volume connected thereto adjoining an exposed surface section of the carrier are covered by an electrically insulating thermal interface structure, which electrically decouples at least one part of the carrier with respect to its surroundings.

公开(公告)号：US10535542B2

公开(公告)日：2020-01-14

申请号：US15662293

申请日：2017-07-28

Applicant: Infineon Technologies AG

Inventor： Andreas Niederhofer ,  Manfred Mengel ,  Holger Tamme ,  Nina Wenger

IPC: B65D73/02 ,  H01L21/677 ,  H01L21/673 ,  H01L21/683

Abstract: Various embodiments provide a wafer box. The wafer box may include a housing with a receiving space for receiving at least one wafer arranged above a housing base, at least one fixing structure which is connected to the housing base and which extends from the housing base, and at least one fixing device which is fastenable to the at least one fixing structure at a variable distance from the housing base. The fixing device and the fixing structure are designed such that the at least one wafer for arrangement in the receiving space can be fixed in a position by means of the at least one fixing device fastened to the fixing structure.

公开(公告)号：US09984897B2

公开(公告)日：2018-05-29

申请号：US15268674

申请日：2016-09-19

Applicant: Infineon Technologies AG

Inventor： Manfred Mengel ,  Joachim Mahler ,  Khalil Hosseini ,  Franz-Peter Kalz

IPC: H01L21/48 ,  H01L23/373 ,  H01L21/77 ,  H01L23/495 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L21/4807 ,  H01L21/4825 ,  H01L21/56 ,  H01L21/77 ,  H01L23/3731 ,  H01L23/3735 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49586 ,  H01L24/27 ,  H01L24/743 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2924/07802 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A chip arrangement is provided, the chip arrangement, including a carrier; a first chip electrically connected to the carrier; a ceramic layer disposed over the carrier; and a second chip disposed over the ceramic layer; wherein the ceramic layer has a porosity in the range from about 3% to about 70%.

公开(公告)号：US09790086B2

公开(公告)日：2017-10-17

申请号：US15268244

申请日：2016-09-16

Applicant: Infineon Technologies AG

Inventor： Franz-Peter Kalz ,  Horst Theuss ,  Bernhard Winkler ,  Khalil Hosseini ,  Joachim Mahler ,  Manfred Mengel

IPC: G01B7/16 ,  B81B7/02 ,  G01L9/00 ,  G01L19/02 ,  G01L19/00 ,  B81B3/00 ,  G01L1/18

CPC classification number: B81B7/02 ,  B81B3/0021 ,  B81B3/0072 ,  B81B2201/0235 ,  B81B2201/0264 ,  B81C2203/0154 ,  G01L1/18 ,  G01L9/0072 ,  G01L19/0092 ,  G01L19/02

Abstract: A micromechanical semiconductor sensing device is disclosed. In an embodiment the sensing device includes a micromechanical sensing structure being configured to yield an electrical sensing signal, and a piezoresistive sensing device provided in the micromechanical sensing structure, the piezoresistive sensing device being arranged to sense a mechanical stress disturbing the electrical sensing signal and being configured to yield an electrical disturbance signal based on the sensed mechanical stress disturbing the electrical sensing signal.

公开(公告)号：US20150279782A1

公开(公告)日：2015-10-01

申请号：US14735604

申请日：2015-06-10

Applicant: Infineon Technologies AG

Inventor： Henrik Ewe ,  Joachim Mahler ,  Manfred Mengel ,  Reimund Engl ,  Josef Hoeglauer ,  Jochen Dangelmaier

IPC: H01L23/538 ,  H01L23/495 ,  H01L21/288 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/5389 ,  H01L21/02282 ,  H01L21/02288 ,  H01L21/288 ,  H01L21/31105 ,  H01L21/4821 ,  H01L21/6835 ,  H01L21/76801 ,  H01L21/76871 ,  H01L21/76877 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49534 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L2221/68345 ,  H01L2224/24011 ,  H01L2224/2402 ,  H01L2224/24051 ,  H01L2224/24137 ,  H01L2224/24145 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/24998 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82001 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/82102 ,  H01L2225/06568 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19043 ,  H01L2924/00 ,  H05K3/4661

Abstract: A semiconductor device is disclosed. One embodiment includes a carrier, a semiconductor chip attached to the carrier, a first conducting line having a first thickness and being deposited over the semiconductor chip and the carrier and a second conducting line having a second thickness and being deposited over the semiconductor chip and the carrier. The first thickness is smaller than the second thickness.

公开(公告)号：US20180033662A1

公开(公告)日：2018-02-01

申请号：US15662295

申请日：2017-07-28

Applicant: Infineon Technologies AG

Inventor： Nina Wenger ,  Manfred Mengel ,  Andreas Niederhofer ,  Holger Tamme

IPC: H01L21/673

Abstract: In various embodiments, a wafer box is provided. The wafer box may include a housing with a receiving space for receiving a stack comprising a plurality of wafers, each arranged above a housing base. The wafers are to be arranged with their main surfaces parallel to the housing base. The receiving space is delimited by the housing base and side walls arranged thereon. The wafer box may further include at least one base opening, arranged in the housing base, for receiving a guide structure of a wafer stacking aid. The guide structure is to be arranged in such a way that, on a side of the housing base on which the side walls are arranged, it extends out of the housing base in order to limit tilting of a wafer raised or lowered in the receiving space in a manner guided by the guide structure.

公开(公告)号：US09559078B2

公开(公告)日：2017-01-31

申请号：US14581653

申请日：2014-12-23

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Manfred Mengel ,  Khalil Hosseini ,  Klaus Schmidt ,  Franz-Peter Kalz

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L24/83 ,  H01L24/00 ,  H01L24/24 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/04026 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/245 ,  H01L2224/2499 ,  H01L2224/26165 ,  H01L2224/27462 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32245 ,  H01L2224/73217 ,  H01L2224/82002 ,  H01L2224/82101 ,  H01L2224/82345 ,  H01L2224/82385 ,  H01L2224/82986 ,  H01L2224/831 ,  H01L2224/83851 ,  H01L2224/92144 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01028 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01047

Abstract: An electronic component includes an electrically conductive carrier. The electrically conductive carrier includes a carrier surface and a semiconductor chip includes a chip surface. One or both of the carrier surface and the chip surface include a non-planar structure. The chip is attached to the carrier with the chip surface facing towards the carrier surface so that a gap is provided between the chip surface and the carrier surface due to the non-planar structure of one or both of the carrier surface and the first chip surface. The electronic component further includes a first galvanically deposited metallic layer situated in the gap.

Abstract translation: 电子部件包括导电载体。 导电载体包括载体表面，半导体芯片包括芯片表面。 载体表面和芯片表面中的一个或两个包括非平面结构。 芯片附着到载体上，其芯片表面面向载体表面，使得由于载体表面和第一芯片表面之一或两者的非平面结构，在芯片表面和载体表面之间提供间隙 。 电子部件还包括位于间隙中的第一电沉积金属层。

公开(公告)号：US20160372393A1

公开(公告)日：2016-12-22

申请号：US15182983

申请日：2016-06-15

Applicant: Infineon Technologies AG

Inventor： Christian Kasztelan ,  Alexander Breymesser ,  Manfred Mengel

IPC: H01L23/29 ,  H01L21/56 ,  H01L21/3105 ,  H01L23/31

Abstract: A method for forming semiconductor devices includes placing a laminar structure having electrically insulating material arranged between a plurality of electrically conductive structures onto a surface of a semiconductor wafer comprising a plurality of semiconductor device structures. An electrically conductive structure of the plurality of electrically conductive structures is located adjacent to a semiconductor device structure of the plurality of semiconductor device structures. Each electrically conductive structure of the plurality of electrically conductive structures extends from a first surface of the laminar structure towards a second opposite surface of the laminar structure.

Abstract translation: 一种用于形成半导体器件的方法包括将具有布置在多个导电结构之间的电绝缘材料的层状结构放置在包括多个半导体器件结构的半导体晶片的表面上。 多个导电结构的导电结构位于多个半导体器件结构的半导体器件结构附近。 多个导电结构的每个导电结构从层状结构的第一表面延伸到层状结构的第二相对表面。