公开(公告)号：US09952511B2

公开(公告)日：2018-04-24

申请号：US15122403

申请日：2014-12-19

Applicant: Intel Corporation

Inventor： Yan A. Borodovsky ,  Donald W. Nelson ,  Mark C. Phillips

IPC: G03F7/20 ,  H01J37/30 ,  H01J37/06 ,  H01J37/147 ,  H01L21/027 ,  H01J37/317 ,  H01L21/311

CPC classification number: G03F7/2037 ,  H01J37/045 ,  H01J37/06 ,  H01J37/1474 ,  H01J37/3007 ,  H01J37/3026 ,  H01J37/3174 ,  H01J37/3177 ,  H01J2237/0435 ,  H01J2237/0453 ,  H01J2237/303 ,  H01J2237/30422 ,  H01J2237/30438 ,  H01J2237/31762 ,  H01J2237/31764 ,  H01J2237/31776 ,  H01J2237/31796 ,  H01L21/0277 ,  H01L21/31144

Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a blanker aperture array (BAA) for an e-beam tool is described. The BAA is a non-universal cutter.

公开(公告)号：US09685436B2

公开(公告)日：2017-06-20

申请号：US14778512

申请日：2013-06-25

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Kimin Jun ,  M. Clair Webb ,  Donald W. Nelson

IPC: H01L27/088 ,  H01L21/84 ,  H01L27/06 ,  H01L27/11 ,  H01L21/8234 ,  H01L27/12 ,  H01L21/768 ,  H01L21/822 ,  H01L23/538 ,  H01L29/78

CPC classification number: H01L27/0688 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/8221 ,  H01L21/823431 ,  H01L21/845 ,  H01L23/5386 ,  H01L27/0886 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1211 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Monolithic 3D ICs employing one or more local inter-level interconnect integrated intimately with at least one structure of at least one transistor on at least one transistor level within the 3D IC. In certain embodiments the local inter-level interconnect intersects a gate electrode or a source/drain region of at least one transistor and extends through at least one inter-level dielectric layer disposed between a first and second transistor level in the 3D IC. Local inter-level interconnects may advantageously make a direct vertical connection between transistors in different levels of the 3D IC without being routed laterally around the footprint (i.e., lateral, or planar, area) of either the overlying or underlying transistor level that is interconnected.

公开(公告)号：US12100762B2

公开(公告)日：2024-09-24

申请号：US17578847

申请日：2022-01-19

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Kimin Jun ,  Il-Seok Son ,  Donald W. Nelson

IPC: H01L29/78 ,  H01L23/00 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L29/417 ,  H01L23/15

CPC classification number: H01L29/78 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/49827 ,  H01L24/00 ,  H01L24/05 ,  H01L29/41791 ,  H01L23/145 ,  H01L23/15 ,  H01L2224/0237 ,  H01L2224/04105 ,  H01L2224/0603 ,  H01L2224/16227

Abstract: An apparatus including a circuit structure including a first side including a device layer including a plurality of devices and an opposite second side; an electrically conductive contact coupled to one of the plurality of devices on the first side; and an electrically conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. A method including forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming an electrically conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact.

公开(公告)号：US10892215B2

公开(公告)日：2021-01-12

申请号：US16408314

申请日：2019-05-09

Applicant: Intel Corporation

Inventor： Donald W. Nelson ,  Mark T. Bohr ,  Patrick Morrow

IPC: H01L23/52 ,  H01L23/498 ,  H01L23/528 ,  H01L49/02

Abstract: An apparatus including a circuit structure including a device stratum; and a contact coupled to a supply line and routed through the device stratum and coupled to at least one device on a first side. A method including providing a supply from a package substrate to at least one transistor in a device stratum of a circuit structure; and distributing the supply to the at least one transistor using a supply line on an underside of the device stratum and contacting the at least one transistor on a device side by routing a contact from the supply line through the device stratum. A system including a package substrate, and a die including at least one supply line disposed on an underside of a device stratum and routed through the device stratum and coupled to at least one of a plurality of transistor devices on the device side.

公开(公告)号：US10700039B2

公开(公告)日：2020-06-30

申请号：US15122382

申请日：2014-06-16

Applicant: Intel Corporation

Inventor： Donald W. Nelson ,  M. Clair Webb ,  Patrick Morrow ,  Kimin Jun

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L21/683 ,  H01L23/498 ,  H01L25/00 ,  H01L23/427

Abstract: A method including forming a plurality of first devices and a plurality of first interconnects on a substrate; coupling a second device layer including a plurality of second devices to ones of the plurality of first interconnects, and forming a plurality of second interconnects on the second device layer. An apparatus including a first device layer including a plurality of first circuit devices disposed between a plurality of first interconnects and a plurality of second interconnects and a second device layer including a plurality of second devices juxtaposed and coupled to one of the plurality of first interconnects and the plurality of second interconnects, wherein one of the plurality of first devices and the plurality of second devices include devices having a higher voltage range than the other of the plurality of first devices and the plurality of second devices.

公开(公告)号：US10325840B2

公开(公告)日：2019-06-18

申请号：US15747988

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Donald W. Nelson ,  Mark T. Bohr ,  Patrick Morrow

IPC: H01L23/50 ,  H01L23/498 ,  H01L23/528 ,  H01L49/02

Abstract: An apparatus including a circuit structure including a device stratum; and a contact coupled to a supply line and routed through the device stratum and coupled to at least one device on a first side. A method including providing a supply from a package substrate to at least one transistor in a device stratum of a circuit structure; and distributing the supply to the at least one transistor using a supply line on an underside of the device stratum and contacting the at least one transistor on a device side by routing a contact from the supply line through the device stratum. A system including a package substrate, and a die including at least one supply line disposed on an underside of a device stratum and routed through the device stratum and coupled to at least one of a plurality of transistor devices on the device side.

公开(公告)号：US10216087B2

公开(公告)日：2019-02-26

申请号：US15122622

申请日：2014-12-19

Applicant: Intel Corporation

Inventor： Yan A. Borodovsky ,  Donald W. Nelson ,  Mark C. Phillips

IPC: G03F7/20 ,  H01L21/027 ,  H01J37/317 ,  H01L21/311

Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a blanker aperture array (BAA) for an e-beam tool includes a first column of openings along a first direction. The BAA also includes a second column of openings along the first direction and staggered from the first column of openings. The first and second columns of openings together form an array having a pitch in the first direction. A scan direction of the BAA is along a second direction, orthogonal to the first direction. The pitch of the array corresponds to half of a minimal pitch layout of a target pattern of lines for orientation parallel with the second direction.

公开(公告)号：US10186484B2

公开(公告)日：2019-01-22

申请号：US15122913

申请日：2014-09-27

Applicant: Intel Corporation

Inventor： Donald W. Nelson ,  Patrick Morrow ,  Kimin Jun

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/00 ,  H01L29/78

Abstract: A method including forming a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and forming contact points to the second plurality of interconnects, the contact points operable for connection to an external source. An apparatus including a substrate including a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and contact points coupled to the second plurality of interconnects, the contact points operable for connection to an external source.

公开(公告)号：US11296197B2

公开(公告)日：2022-04-05

申请号：US15746799

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Donald W. Nelson

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

Abstract: An apparatus including a circuit structure including a device stratum including a plurality of transistor devices each including a first side defined by a gate electrode and an opposite second side; and a gated supply grid disposed on the second side of the structure, wherein a drain of the at least one of the plurality of transistor devices is coupled to the gated supply grid. A method including providing a supply from a package substrate to power gate transistors in a device layer of a circuit structure, the transistors coupled to circuitry operable to receive a gated supply from the power gate transistors; and distributing the gated supply from the power gate transistors to the circuitry using a grid on an underside of the device layer.

公开(公告)号：US10578970B2

公开(公告)日：2020-03-03

申请号：US16252427

申请日：2019-01-18

Applicant: Intel Corporation

Inventor： Yan A. Borodovsky ,  Donald W. Nelson ,  Mark C. Phillips

IPC: G03F7/20 ,  H01L21/027 ,  H01L21/311 ,  H01J37/302 ,  H01J37/317 ,  H01J37/04

Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a blanker aperture array (BAA) for an e-beam tool includes a first column of openings along a first direction. The BAA also includes a second column of openings along the first direction and staggered from the first column of openings. The first and second columns of openings together form an array having a pitch in the first direction. A scan direction of the BAA is along a second direction, orthogonal to the first direction. The pitch of the array corresponds to half of a minimal pitch layout of a target pattern of lines for orientation parallel with the second direction.