公开(公告)号：US10777538B2

公开(公告)日：2020-09-15

申请号：US16399726

申请日：2019-04-30

Applicant: INTEL CORPORATION

Inventor： Fay Hua ,  Telesphor Kamgaing ,  Johanna M. Swan

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L21/02 ,  H01L23/29 ,  H01L23/64 ,  H01L21/768 ,  H01L23/66 ,  H01L23/522

Abstract: Embodiments include devices and methods, including a device including a substrate comprising a semiconductor, the substrate including a front side comprising active elements and a backside opposite the front side. The device includes a dielectric layer on the backside, and a passive component on the dielectric layer on the backside. In certain embodiments, the passive device is formed on a self-assembled monolayer (SAM). Other embodiments are described and claimed.

公开(公告)号：US20180096975A1

公开(公告)日：2018-04-05

申请号：US15282473

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Fay Hua ,  Robert L. Sankman

IPC: H01L25/10 ,  H01L23/29 ,  H01L23/498 ,  H01L21/48 ,  H01L25/00 ,  H01L23/00

Abstract: A high density package on package electrical device is disclosed. The electrical device comprises a first integrated circuit package comprising a substrate, an integrated circuit component attached to the substrate, and a molding compound covering the component, wherein the top of the molding compound has a redistribution layer of metal covering at least part of the molding compound. The device further comprises a second integrated circuit package including a second substrate, a semiconductor component attached to the substrate, and a molding compound covering the electronic component, wherein the bottom of the substrate includes metal contacts for communication between the second integrated circuit package and other components. The device further comprises a solder layer that connects the top of the first integrated circuit package to the bottom of the second electric package by connecting the metal of the redistribution layer to the metal connections on the bottom of the second substrate.

公开(公告)号：US09824962B1

公开(公告)日：2017-11-21

申请号：US15279708

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Fay Hua ,  Adel A. Elsherbini

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L21/4846 ,  H01L21/486 ,  H01L23/145 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/24 ,  H01L2224/24151 ,  H01L2224/245 ,  H05K3/185 ,  H05K2203/072 ,  H05K2203/107 ,  H05K2203/122

Abstract: Methods of forming microelectronic package structures are described. Those methods/structures may include forming a high density region on a board comprising a first plurality of conductive structures disposed on a dielectric material on the board, wherein the first plurality of conductive structures comprises a first pitch between individual ones of the first plurality of conductive structures. A low density region on the board comprises a second plurality of conductive structures disposed on the dielectric material, wherein the second plurality of conductive structures comprises a second pitch between individual ones of the second plurality of conductive structures, wherein the second pitch is more than about twice the magnitude of the first pitch.

公开(公告)号：US20170053858A1

公开(公告)日：2017-02-23

申请号：US14831528

申请日：2015-08-20

Applicant: INTEL CORPORATION

Inventor： Jan Krajniak ,  Carl L. Deppisch ,  Kabirkumar J. Mirpuri ,  Hongjin Jiang ,  Fay Hua ,  Yuying Wei ,  Beverly J. Canham ,  Jiongxin Lu ,  Mukul P. Renavikar

IPC: H01L23/498 ,  B23K1/20 ,  B23K35/02 ,  H01L21/48 ,  B23K35/26 ,  B23K35/30 ,  H01L23/00 ,  B23K1/00 ,  B23K35/36

CPC classification number: H01L23/49833 ,  B23K1/0016 ,  B23K3/0623 ,  B23K35/025 ,  B23K35/262 ,  B23K35/264 ,  B23K35/3006 ,  B23K35/302 ,  B23K35/3613 ,  H01L21/4867 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/11334 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13017 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/13311 ,  H01L2224/1339 ,  H01L2224/13565 ,  H01L2224/136 ,  H01L2224/1369 ,  H01L2224/1601 ,  H01L2224/16058 ,  H01L2224/16227 ,  H01L2224/81594 ,  H01L2224/816 ,  H01L2224/81611 ,  H01L2224/8169 ,  H01L2224/81815 ,  H01L2224/81862 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/15331 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/3841 ,  H05K1/141 ,  H05K3/363 ,  H05K2201/10378 ,  H05K2201/10734 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01083 ,  H01L2924/01028 ,  H01L2924/01025 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01038 ,  H01L2924/01024 ,  H01L2924/01022 ,  H01L2924/05341 ,  H01L2924/0665 ,  H01L2924/00012

Abstract: Embodiments herein may relate to a patch on interposer (PoINT) architecture. In embodiments, the PoINT architecture may include a plurality of solder joints between a patch and an interposer. The solder joints may include a relatively high temperature solder ball and a relatively low temperature solder paste that at least partially surrounds the solder ball. Other embodiments may be described and/or claimed.

Abstract translation: 这里的实施例可以涉及内插器（PoINT）架构上的补丁。 在实施例中，PoINT架构可以包括贴片和插入器之间的多个焊接点。 焊点可以包括相对高温的焊球和至少部分地围绕焊料球的相对低温的焊膏。 可以描述和/或要求保护其他实施例。