公开(公告)号：US09394619B2

公开(公告)日：2016-07-19

申请号：US13795042

申请日：2013-03-12

Applicant: Intel Corporation

Inventor： Rajen S. Sidhu ,  Mukul P. Renavikar ,  Sandeep B. Sane

IPC: H05K1/09 ,  H05K1/03 ,  C25D3/58 ,  C25D5/02 ,  H05K3/42 ,  H05K3/46 ,  C23C18/48

CPC classification number: C25D3/58 ,  C23C18/48 ,  C25D5/02 ,  H05K3/421 ,  H05K3/4644

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include forming an opening in a dielectric material of a package substrate, and then plating a conductive interconnect structure in the opening utilizing a plating process. The plating process may comprises a conductive metal and a dopant comprising between about 0.05 and 10 percent weight, wherein the dopant comprises at least one of magnesium, zirconium and zinc.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法和结构可以包括在封装衬底的电介质材料中形成开口，然后使用电镀工艺在开口中镀覆导电互连结构。 电镀工艺可以包括导电金属和掺杂剂，其包含约0.05至10重量％的重量，其中掺杂剂包括镁，锆和锌中的至少一种。

公开(公告)号：US10049971B2

公开(公告)日：2018-08-14

申请号：US15478064

申请日：2017-04-03

Applicant: Intel Corporation

Inventor： Thomas J. De Bonis ,  Lilia May ,  Rajen S. Sidhu ,  Mukul P. Renavikar ,  Ashay A. Dani ,  Edward R. Prack ,  Carl L. Deppisch ,  Anna M. Prakash ,  James C. Matayabas ,  Jason Jieping Zhang ,  Srinivasa R. Aravamudhan ,  Chang Lin

IPC: H01L21/00 ,  H01L23/498 ,  H01L25/065 ,  H01L23/31 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L25/00 ,  H01L23/00

Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.

公开(公告)号：US20170053858A1

公开(公告)日：2017-02-23

申请号：US14831528

申请日：2015-08-20

Applicant: INTEL CORPORATION

Inventor： Jan Krajniak ,  Carl L. Deppisch ,  Kabirkumar J. Mirpuri ,  Hongjin Jiang ,  Fay Hua ,  Yuying Wei ,  Beverly J. Canham ,  Jiongxin Lu ,  Mukul P. Renavikar

IPC: H01L23/498 ,  B23K1/20 ,  B23K35/02 ,  H01L21/48 ,  B23K35/26 ,  B23K35/30 ,  H01L23/00 ,  B23K1/00 ,  B23K35/36

CPC classification number: H01L23/49833 ,  B23K1/0016 ,  B23K3/0623 ,  B23K35/025 ,  B23K35/262 ,  B23K35/264 ,  B23K35/3006 ,  B23K35/302 ,  B23K35/3613 ,  H01L21/4867 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/11334 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13017 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/13311 ,  H01L2224/1339 ,  H01L2224/13565 ,  H01L2224/136 ,  H01L2224/1369 ,  H01L2224/1601 ,  H01L2224/16058 ,  H01L2224/16227 ,  H01L2224/81594 ,  H01L2224/816 ,  H01L2224/81611 ,  H01L2224/8169 ,  H01L2224/81815 ,  H01L2224/81862 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/15331 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/3841 ,  H05K1/141 ,  H05K3/363 ,  H05K2201/10378 ,  H05K2201/10734 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01083 ,  H01L2924/01028 ,  H01L2924/01025 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01038 ,  H01L2924/01024 ,  H01L2924/01022 ,  H01L2924/05341 ,  H01L2924/0665 ,  H01L2924/00012

Abstract: Embodiments herein may relate to a patch on interposer (PoINT) architecture. In embodiments, the PoINT architecture may include a plurality of solder joints between a patch and an interposer. The solder joints may include a relatively high temperature solder ball and a relatively low temperature solder paste that at least partially surrounds the solder ball. Other embodiments may be described and/or claimed.

Abstract translation: 这里的实施例可以涉及内插器（PoINT）架构上的补丁。 在实施例中，PoINT架构可以包括贴片和插入器之间的多个焊接点。 焊点可以包括相对高温的焊球和至少部分地围绕焊料球的相对低温的焊膏。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20170207152A1

公开(公告)日：2017-07-20

申请号：US15478064

申请日：2017-04-03

Applicant: Intel Corporation

Inventor： Thomas J. De Bonis ,  Lilia May ,  Rajen S. Sidhu ,  Mukul P. Renavikar ,  Ashay A. Dani ,  Edward R. Prack ,  Carl L. Deppisch ,  Anna M. Prakash ,  James C. Matayabas ,  Jason Jieping Zhang ,  Srinivasa R. Aravamudhan ,  Chang Lin

IPC: H01L23/498 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/76802 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13023 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/37001 ,  H01L2924/00

Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.