公开(公告)号：US11916003B2

公开(公告)日：2024-02-27

申请号：US16575307

申请日：2019-09-18

Applicant: Intel Corporation

Inventor： Xiao Lu ,  Jiongxin Lu ,  Christopher Combs ,  Alexander Huettis ,  John Harper ,  Jieping Zhang ,  Nachiket R. Raravikar ,  Pramod Malatkar ,  Steven A. Klein ,  Carl Deppisch ,  Mohit Sood

IPC: H01L23/48 ,  B23K3/06 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L23/49833 ,  B23K3/0623 ,  H01L23/49822 ,  H01L23/4985 ,  H01L23/5387

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate; a second substrate; and an array of interconnects electrically coupling the first substrate to the second substrate. In an embodiment, the array of interconnects comprises first interconnects, wherein the first interconnects have a first volume and a first material composition, and second interconnects, wherein the second interconnects have a second volume and a second material composition, and wherein the first volume is different than the second volume and/or the first material composition is different than the second material composition.

公开(公告)号：US20170053858A1

公开(公告)日：2017-02-23

申请号：US14831528

申请日：2015-08-20

Applicant: INTEL CORPORATION

Inventor： Jan Krajniak ,  Carl L. Deppisch ,  Kabirkumar J. Mirpuri ,  Hongjin Jiang ,  Fay Hua ,  Yuying Wei ,  Beverly J. Canham ,  Jiongxin Lu ,  Mukul P. Renavikar

IPC: H01L23/498 ,  B23K1/20 ,  B23K35/02 ,  H01L21/48 ,  B23K35/26 ,  B23K35/30 ,  H01L23/00 ,  B23K1/00 ,  B23K35/36

CPC classification number: H01L23/49833 ,  B23K1/0016 ,  B23K3/0623 ,  B23K35/025 ,  B23K35/262 ,  B23K35/264 ,  B23K35/3006 ,  B23K35/302 ,  B23K35/3613 ,  H01L21/4867 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/11334 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13017 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/13311 ,  H01L2224/1339 ,  H01L2224/13565 ,  H01L2224/136 ,  H01L2224/1369 ,  H01L2224/1601 ,  H01L2224/16058 ,  H01L2224/16227 ,  H01L2224/81594 ,  H01L2224/816 ,  H01L2224/81611 ,  H01L2224/8169 ,  H01L2224/81815 ,  H01L2224/81862 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/15331 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/3841 ,  H05K1/141 ,  H05K3/363 ,  H05K2201/10378 ,  H05K2201/10734 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01083 ,  H01L2924/01028 ,  H01L2924/01025 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01038 ,  H01L2924/01024 ,  H01L2924/01022 ,  H01L2924/05341 ,  H01L2924/0665 ,  H01L2924/00012

Abstract: Embodiments herein may relate to a patch on interposer (PoINT) architecture. In embodiments, the PoINT architecture may include a plurality of solder joints between a patch and an interposer. The solder joints may include a relatively high temperature solder ball and a relatively low temperature solder paste that at least partially surrounds the solder ball. Other embodiments may be described and/or claimed.

Abstract translation: 这里的实施例可以涉及内插器（PoINT）架构上的补丁。 在实施例中，PoINT架构可以包括贴片和插入器之间的多个焊接点。 焊点可以包括相对高温的焊球和至少部分地围绕焊料球的相对低温的焊膏。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20190304805A1

公开(公告)日：2019-10-03

申请号：US15941809

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Jiongxin Lu ,  Aravindha Antoniswamy ,  Jinlin Wang ,  Ashutosh Srivastava

IPC: H01L21/48 ,  H01L23/498

Abstract: An electronic package including a substrate. The substrate includes a first solder material that is applied adjacent a periphery of the substrate. The substrate also includes a second solder material having properties different than the first solder material that is applied adjacent a periphery of a keep in zone of the substrate.