公开(公告)号：US20210305121A1

公开(公告)日：2021-09-30

申请号：US16831068

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Je-Young Chang ,  Ram Viswanath ,  Elah Bozorg-Grayeli ,  Ahmad Al Mohammad

IPC: H01L23/367 ,  H01L23/538 ,  H01L23/00 ,  H01L23/373 ,  H01L23/18 ,  H01L21/48

Abstract: Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.

公开(公告)号：US20200294884A1

公开(公告)日：2020-09-17

申请号：US16355596

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Javed Shaikh ,  Je-Young Chang ,  Kelly Lofgreen ,  Weihua Tang ,  Aastha Uppal

IPC: H01L23/38 ,  H01L35/10 ,  H01L35/16 ,  H01L35/18 ,  H01L35/30

Abstract: An Integrated Circuit (IC) assembly, comprising an IC package coupled to a substrate, and a subassembly comprising a thermal interface layer. The thermal interface layer comprises a phase change material (PCM) over the IC package. At least one thermoelectric cooling (TEC) apparatus is thermally coupled to the thermal interface layer.

公开(公告)号：US10600699B2

公开(公告)日：2020-03-24

申请号：US15685772

申请日：2017-08-24

Applicant: Intel Corporation

Inventor： Aastha Uppal ,  Je-Young Chang ,  Shankar Devasenathipathy ,  Joseph B. Petrini

IPC: H01L21/66 ,  G01K7/22 ,  H01L23/498 ,  G01K1/02 ,  G01K1/14 ,  H01L23/427

Abstract: Embodiments of the present disclosure provide techniques and configurations for inspection of a package assembly with a thermal solution, in accordance with some embodiments. In embodiments, an apparatus for inspection of a package assembly with a thermal solution may include a first fixture to house the package assembly on the apparatus, and a second fixture to house at least a portion of a thermal solution that is to be disposed on top of the package assembly. The apparatus may further include a load actuator, to apply a load to a die of the package assembly, via the thermal solution, and a plurality of sensors disposed around the thermal solution and the package assembly, to perform in situ thermal and/or mechanical measurements associated with the application of the load to the die of the package assembly. Other embodiments may be described and/or claimed.

公开(公告)号：US12238892B2

公开(公告)日：2025-02-25

申请号：US17128620

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Raanan Sover ,  James Williams ,  Bradley Smith ,  Nir Peled ,  Paul George ,  Jason Armstrong ,  Alexey Chinkov ,  Meir Cohen ,  Je-Young Chang ,  Kuang Liu ,  Ravindranath Mahajan ,  Kelly Lofgreen ,  Kyle Arrington ,  Michael Crocker ,  Sergio Antonio Chan Arguedas

IPC: H05K7/20

Abstract: A two-phase immersion cooling system for an integrated circuit assembly may be formed utilizing boiling enhancement structures formed on or directly attached to heat dissipation devices within the integrated circuit assembly, formed on or directly attached to integrated circuit devices within the integrated circuit assembly, and/or conformally formed over support devices and at least a portion of an electronic board within the integrated circuit assembly. In still a further embodiment, the two-phase immersion cooling system may include a low boiling point liquid including at least two liquids that are substantially immiscible with one another.

公开(公告)号：US12046536B2

公开(公告)日：2024-07-23

申请号：US16398452

申请日：2019-04-30

Applicant: Intel Corporation

Inventor： Je-Young Chang ,  James C. Matayabas, Jr. ,  Zhimin Wan ,  Kyle Arrington

IPC: H01L23/473 ,  H01L23/367 ,  H01L23/373 ,  H05K7/20

CPC classification number: H01L23/473 ,  H01L23/367 ,  H01L23/3733 ,  H05K7/20309 ,  H05K7/20327 ,  H05K7/20336

Abstract: An integrated circuit package includes a first die and second die above a substrate, and a vapor chamber above at least one of the first and second die. A vapor space within the vapor chamber is separated into at least a first section and a second section. The first section may be over the first die, and the second section may be over the second die, for example. The structure separating the first and second sections at least partly restricts flow of vapor between the first and second sections, thereby preventing or reducing thermal cross talk between the first and second dies. In some cases, an anisotropic thermal material is above one of the first or second die, wherein the anisotropic thermal material has substantially higher thermal conductivity in a direction of a heat sink than a thermal conductivity in a direction of a section of the vapor chamber.

公开(公告)号：US11984377B2

公开(公告)日：2024-05-14

申请号：US16831068

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Je-Young Chang ,  Ram Viswanath ,  Elah Bozorg-Grayeli ,  Ahmad Al Mohammad

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L23/18 ,  H01L23/373 ,  H01L23/538

CPC classification number: H01L23/3675 ,  H01L21/4875 ,  H01L23/18 ,  H01L23/3735 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/1432 ,  H01L2924/1434

Abstract: Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.

公开(公告)号：US11923267B2

公开(公告)日：2024-03-05

申请号：US16831076

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Je-Young Chang ,  Ram Viswanath ,  Elah Bozorg-Grayeli ,  Ahmad Al Mohammad

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/495

CPC classification number: H01L23/3672 ,  H01L23/373 ,  H01L23/49568

Abstract: Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.

公开(公告)号：US11901262B2

公开(公告)日：2024-02-13

申请号：US16256831

申请日：2019-01-24

Applicant: Intel Corporation

Inventor： Nicholas Neal ,  Zhimin Wan ,  Shankar Devasenathipathy ,  Je-Young Chang

IPC: H01L23/433 ,  F28F19/01 ,  H01L21/48

CPC classification number: H01L23/4336 ,  F28F19/01 ,  H01L21/4882

Abstract: Embodiments include a cooling solution having a first array of fins, where the first array of fins extend vertically from the substrate, and where adjacent individual fins of the first array are separated from each other by a microchannel. A second array of fins extend vertically from the substrate, where a channel region is between the first array of fins and the second array of fins.

公开(公告)号：US11854932B2

公开(公告)日：2023-12-26

申请号：US16721122

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Feras Eid ,  Chandra Mohan Jha ,  Je-Young Chang

IPC: H01L23/36 ,  H01L23/367 ,  H01L23/373 ,  H01L23/48

CPC classification number: H01L23/3672 ,  H01L23/373 ,  H01L23/481

Abstract: Embodiments disclosed herein include electronic packages and thermal solutions for such electronic packages. In an embodiment, an electronic package comprises, a package substrate with a first surface, a second surface opposite from the first surface, and a sidewall surface connecting the first surface to the second surface. In an embodiment, the electronic package further comprises a heat spreader, where a first portion of the heat spreader is attached to the first surface of the package substrate and a second portion of the heat spreader is attached to the second surface of the package substrate. In an embodiment, a third portion of the heat spreader adjacent to the sidewall surface of the package substrate connects the first portion of the heat spreader to the second portion of the heat spreader.

公开(公告)号：US11508645B2

公开(公告)日：2022-11-22

申请号：US16636296

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Chandra M. Jha ,  Je-Young Chang

IPC: H01L23/473 ,  H01L23/373 ,  H01L23/40

Abstract: An integrated circuit assembly including a first die including a device side and a backside opposite the device side; and a second die including a plurality of fluidly accessible channels therein, wherein the second die is coupled to a backside of the first die. A method of fabricating an integrated circuit assembly including coupling a first die to a second die, wherein the first die includes a device side and an opposite backside, wherein the device side includes a plurality of integrated circuits and wherein the second die includes a plurality of fluidly accessible channels therein.