公开(公告)号：US20170060681A1

公开(公告)日：2017-03-02

申请号：US14998184

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： John B. Halbert ,  Kuljit S. Bains

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC classification number: G06F11/1048 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068 ,  G11C11/401 ,  G11C29/42 ,  G11C29/52 ,  H03M13/095 ,  H03M13/6566

Abstract: An error check and scrub (ECS) mode enables a memory device to perform error checking and correction (ECC) and count errors. An associated memory controller triggers the ECS mode with a trigger sent to the memory device. The memory device includes multiple addressable memory locations, which can be organized in segments such as wordlines. The memory locations store data and have associated ECC information. In the ECS mode, the memory device reads one or more memory locations and performs ECC for the one or more memory locations based on the ECC information. The memory device counts error information including a segment count indicating a number of segments having at least a threshold number of errors, and a maximum count indicating a maximum number of errors in any segment.

Abstract translation: 错误检查和擦除（ECS）模式使存储器件能够执行错误检查和校正（ECC）并计数错误。 相关联的存储器控​​制器通过触发发送到存储器件的触发器来触发ECS模式。 存储器件包括多个可寻址的存储器位置，其可以被组织成诸如字线的段。 存储器位置存储数据并具有相关联的ECC信息。 在ECS模式中，存储器件读取一个或多个存储器位置，并且基于ECC信息为一个或多个存储器位置执行ECC。 存储器装置对包括指示具有至少阈值数量的错误的段的数量的段计数以及指示任何段中的最大错误数的最大计数的错误信息进行计数。

公开(公告)号：US09564201B2

公开(公告)日：2017-02-07

申请号：US15011286

申请日：2016-01-29

Applicant: Intel Corporation

Inventor： John B. Halbert ,  Kuljit S. Bains

IPC: G11C11/406 ,  G11C11/4076 ,  G06F12/06 ,  G11C7/10

CPC classification number: G11C11/40618 ,  G06F3/0616 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0646 ,  G06F12/0684 ,  G11C7/1072 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/4076

Abstract: Techniques and mechanisms to facilitate an operational mode of a memory device to prepare for a targeted refresh of a row in memory. In an embodiment, the memory device performs one or more operations while in the mode to prepare for a future command from a memory controller, the command to implement, at least in part, a targeted refresh of a row in a first bank of the memory device. Prior to such a command, the memory device services another command from the memory controller. In another embodiment, servicing the other command includes the memory device accessing a second bank of the memory device while the memory device operates in the mode, and before completion of an expected future targeted row refresh.

Abstract translation: 促进存储器设备的操作模式以准备存储器中的行的目标刷新的技术和机制。 在一个实施例中，存储器装置在处于来自存储器控制器的未来命令的模式中执行一个或多个操作，该命令至少部分地实现存储器的第一存储体中的行的目标刷新 设备。 在这样的命令之前，存储器设备从存储器控制器服务另一命令。 在另一个实施例中，服务另一个命令包括存储设备访问存储器设备的第二组，同时存储设备在模式下操作，并且在预期的未来目标行刷新完成之前。

公开(公告)号：US20160379690A1

公开(公告)日：2016-12-29

申请号：US15225717

申请日：2016-08-01

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  Klaus RUFF ,  George VERGIS ,  Suneeta SAH

IPC: G11C7/10

CPC classification number: G11C7/1072 ,  G06F11/073 ,  G06F11/0787 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1016 ,  G06F11/1612 ,  G06F13/16 ,  G06F13/28 ,  G11C7/1006 ,  G11C29/44 ,  G11C2029/0411 ,  G11C2029/4402

Abstract: A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.

公开(公告)号：US20160350180A1

公开(公告)日：2016-12-01

申请号：US14865956

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： John B. Halbert ,  Kuljit S. Bains

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G11C11/40 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52 ,  G11C29/56008 ,  G11C2029/0411

Abstract: A memory subsystem enables managing error correction information. A memory device internally performs error detection for a range of memory locations, and increments an internal count for each error detected. The memory device includes ECC logic to generate an error result indicating a difference between the internal count and a baseline number of errors preset for the memory device. The memory device can provide the error result to an associated host of the system to expose only a number of errors accumulated without exposing internal errors from prior to incorporation into a system. The memory device can be made capable to generate internal addresses to execute commands received from the memory controller. The memory device can be made capable to reset the counter after a first pass through the memory area in which errors are counted.

Abstract translation: 存储器子系统能够管理纠错信息。 内存设备内部对一系列内存位置执行错误检测，并为检测到的每个错误增加内部计数。 存储器件包括ECC逻辑，用于产生指示内存计数与为存储器件预设的基准线数之间的差异的错误结果。 存储器装置可以向系统的相关联的主机提供错误结果，以仅暴露出许多累积的错误，而不会将内部错误暴露于系统之前。 可以使存储器件能够产生内部地址以执行从存储器控制器接收的命令。 可以使存储器件能够在首次通过其中计数错误的存储区域之后复位计数器。

公开(公告)号：US20160284386A1

公开(公告)日：2016-09-29

申请号：US14670411

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： James A. McCall ,  Kuljit S. Bains

IPC: G11C7/10 ,  G11C29/50 ,  G06F11/30 ,  G06F13/42

CPC classification number: G06F11/3089 ,  G06F11/3037 ,  G06F11/3058 ,  G06F13/4243 ,  G11C7/1057 ,  G11C7/1084 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50008

Abstract: A memory subsystem manages memory I/O impedance compensation by the memory device monitoring a need for impedance compensation. Instead of a memory controller regularly sending a signal to have the memory device update the impedance compensation when a change is not needed, the memory device can indicate when it is ready to perform an impedance compensation change. The memory controller can send an impedance compensation signal to the memory device in response to a compensation flag set by the memory or in response to determining that a sensor value has changed in excess of a threshold.

Abstract translation: 存储器子系统通过存储器件管理存储器I / O阻抗补偿，监测对阻抗补偿的需要。 代替存储器控制器定期发送信号以使得存储器件在不需要改变时更新阻抗补偿，存储器件可以指示何时准备好进行阻抗补偿改变。 存储器控制器可以响应于由存储器设置的补偿标志或响应于确定传感器值已经改变超过阈值而向阻塞补偿信号发送阻抗补偿信号。

公开(公告)号：US20160188257A1

公开(公告)日：2016-06-30

申请号：US14952324

申请日：2015-11-25

Applicant: Intel Corporation

Inventor： Christopher P. Mozak ,  Kuljit S. Bains

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0608 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0634 ,  G06F3/0673 ,  G06F3/068 ,  G06F11/2094 ,  G06F2201/805 ,  G11C7/1045 ,  G11C7/24 ,  G11C29/025 ,  G11C29/46 ,  G11C29/50012 ,  G11C29/70 ,  G11C29/76 ,  G11C29/83

Abstract: In an embodiment, a memory device may contain device processing logic and a mode register. The mode register may a register that may specify a mode of operation of the memory device. A field in the mode register may hold a value that may indicate whether a command associated with the memory device is disabled. The value may be held in the field until either the memory device is power-cycled or reset. The device processing logic may acquire an instance of the command. The device processing logic may determine whether the command is disabled based on the value held by the mode register. The device processing logic may not execute the instance of the command if the device processing logic determines the command is disabled. If the device processing logic determines the command is not disabled, the device processing logic may execute the instance of the command.

公开(公告)号：US09286964B2

公开(公告)日：2016-03-15

申请号：US13725800

申请日：2012-12-21

Applicant: Intel Corporation

Inventor： John B. Halbert ,  Kuljit S. Bains

IPC: G11C11/406 ,  G11C11/4076

CPC classification number: G11C11/40618 ,  G06F3/0616 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0646 ,  G06F12/0684 ,  G11C7/1072 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/4076

Abstract: Techniques and mechanisms to facilitate an operational mode of a memory device to prepare for a targeted refresh of a row in memory. In an embodiment, the memory device performs one or more operations while in the mode to prepare for a future command from a memory controller, the command to implement, at least in part, a targeted refresh of a row in a first bank of the memory device. Prior to such a command, the memory device services another command from the memory controller. In another embodiment, servicing the other command includes the memory device accessing a second bank of the memory device while the memory device operates in the mode, and before completion of an expected future targeted row refresh.

Abstract translation: 促进存储器设备的操作模式以准备存储器中的行的目标刷新的技术和机制。 在一个实施例中，存储器装置在处于来自存储器控制器的未来命令的模式中执行一个或多个操作，该命令至少部分地实现存储器的第一存储体中的行的目标刷新 设备。 在这样的命令之前，存储器设备从存储器控制器服务另一命令。 在另一个实施例中，服务另一个命令包括存储设备访问存储器设备的第二组，同时存储设备在模式下操作，并且在预期的未来目标行刷新完成之前。

公开(公告)号：US09117542B2

公开(公告)日：2015-08-25

申请号：US14039768

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Kuljit S. Bains

IPC: G11C7/00 ,  G11C11/406

CPC classification number: G11C11/40615 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40618

Abstract: A memory device includes a per bank refresh counter applicable to multiple banks in a group. The memory device increments a row address counter only when the per bank refresh counter is reset. The memory device receives a per bank refresh command from an associated memory controller, and performs a per bank refresh in response to receiving the per bank refresh command. The memory device refreshes a row identified by a row address counter for a bank identified by the per bank refresh command. The memory device increments the per bank refresh counter in response to receiving the per bank refresh command, and increments the row address counter when the per bank refresh counter is reset, either by rolling over or by a reset condition.

Abstract translation: 存储器装置包括适用于组中的多个银行的每个银行刷新计数器。 只有当每个存储体刷新计数器复位时，存储器才会递增行地址计数器。 存储器装置从相关联的存储器控​​制器接收每个存储体刷新命令，并且响应于接收每个存储体刷新命令执行每个存储体刷新。 存储器件刷新由用于由每个存储体刷新命令标识的存储体的行地址计数器标识的一行。 响应于接收到每个刷新命令，存储器件增加每个存储体刷新计数器，并且当通过翻转或通过复位条件复位每个存储体刷新计数器时递增行地址计数器。

公开(公告)号：US20140177370A1

公开(公告)日：2014-06-26

申请号：US13725800

申请日：2012-12-21

Applicant: INTEL CORPORATION

Inventor： John B. Halbert ,  Kuljit S. Bains

IPC: G11C11/402

CPC classification number: G11C11/40618 ,  G06F3/0616 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0646 ,  G06F12/0684 ,  G11C7/1072 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/4076

Abstract: Techniques and mechanisms to facilitate an operational mode of a memory device to prepare for a targeted refresh of a row in memory. In an embodiment, the memory device performs one or more operations while in the mode to prepare for a future command from a memory controller, the command to implement, at least in part, a targeted refresh of a row in a first bank of the memory device. Prior to such a command, the memory device services another command from the memory controller. In another embodiment, servicing the other command includes the memory device accessing a second bank of the memory device while the memory device operates in the mode, and before completion of an expected future targeted row refresh.

Abstract translation: 促进存储器设备的操作模式以准备存储器中的行的目标刷新的技术和机制。 在一个实施例中，存储器装置在处于来自存储器控制器的未来命令的模式中执行一个或多个操作，该命令至少部分地实现存储器的第一存储体中的行的目标刷新 设备。 在这样的命令之前，存储器设备从存储器控制器服务另一命令。 在另一个实施例中，服务另一个命令包括存储设备访问存储器设备的第二组，同时存储设备在模式下操作，并且在预期的未来目标行刷新完成之前。

公开(公告)号：US20240222347A1

公开(公告)日：2024-07-04

申请号：US18148338

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Kuljit S. Bains ,  Wilfred Gomes ,  Don Douglas Josephson ,  Surhud V. Khare ,  Christopher Philip Mozak ,  Randy B. Osborne ,  Pushkar Ranade ,  Abhishek Anil Sharma

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H10B80/00

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L24/16 ,  H10B80/00 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: In embodiments herein, an integrated circuit device includes a logic die with processor circuitry and a memory die coupled to the logic die. The memory die includes a first memory module comprising a first memory bank and first control circuitry, a second memory module comprising a second memory bank and second control circuitry, and a scribe line on a surface of the memory die between the first memory module and the second memory module. The first memory module is not electrically connected to the second memory module, and each memory module include through silicon vias (TSVs) to electrically connect a top side of the memory module and a bottom side of the memory module (e.g., for three-dimensional stacking in the integrated circuit device).