公开(公告)号：US20230307373A1

公开(公告)日：2023-09-28

申请号：US18202136

申请日：2023-05-25

Applicant: Intel Corporation

Inventor： Mathew J. MANUSHAROW ,  Jonathan ROSENFELD

IPC: H01L23/538 ,  H01L25/065 ,  H01L21/48 ,  H01L23/498 ,  H01L23/64 ,  H01L25/00

CPC classification number: H01L23/5383 ,  H01L25/065 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/642 ,  H01L23/647 ,  H01L25/0655 ,  H01L25/50 ,  H01L2924/15192 ,  H01L2224/16235 ,  H01L2224/16227 ,  H01L23/5385 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L24/16

Abstract: An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.

公开(公告)号：US20220115326A1

公开(公告)日：2022-04-14

申请号：US17555213

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Mathew J. MANUSHAROW ,  Jonathan ROSENFELD

IPC: H01L23/538 ,  H01L25/065 ,  H01L21/48 ,  H01L23/498 ,  H01L23/64 ,  H01L25/00

Abstract: An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.

公开(公告)号：US20180332708A1

公开(公告)日：2018-11-15

申请号：US15774263

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： William J. LAMBERT ,  Mihir K. ROY ,  Mathew J. MANUSHAROW

IPC: H05K1/18 ,  H01L25/16 ,  H01L23/498 ,  H01L21/48 ,  H05K3/00 ,  H05K3/40

CPC classification number: H05K1/185 ,  H01L21/486 ,  H01L23/49827 ,  H01L25/16 ,  H05K1/181 ,  H05K3/0047 ,  H05K3/3436 ,  H05K3/4038 ,  H05K2201/10015 ,  H05K2201/1003 ,  H05K2201/10454 ,  H05K2201/10515 ,  H05K2201/10651

Abstract: Embodiments are generally directed to vertically embedded passive components. An embodiment of a device includes a semiconductor die; and a package coupled with the semiconductor die. The package includes one or more passive components connected with the semiconductor die, the one or more passive components being embedded vertically in the package substrate, each of the passive components including a first terminal and a second terminal. A first passive component is embedded in a through hole drilled in the package, the first terminal of the first passive component being connected to the semiconductor die by a via through an upper buildup layer on the package.

公开(公告)号：US20180315690A1

公开(公告)日：2018-11-01

申请号：US15773030

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Mathew J. MANUSHAROW ,  Krishna BHARATH ,  William J. LAMBERT ,  Robert L. SANKMAN ,  Aleksandar ALEKSOV ,  Brandon M. RAWLINGS ,  Feras EID ,  Javier SOTO GONZALEZ ,  Meizi JIAO ,  Suddhasattwa NAD ,  Telesphor KAMGAING

IPC: H01L23/498 ,  H01F27/28 ,  H01L49/02 ,  H01F41/04 ,  H01L21/48 ,  H01G4/33 ,  H01L23/66

CPC classification number: H01F27/40 ,  H01F17/0006 ,  H01L28/00

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

公开(公告)号：US20170092573A1

公开(公告)日：2017-03-30

申请号：US14866491

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： Mathew J. MANUSHAROW ,  Daniel N. SOBIESKI ,  Mihir K. ROY ,  William J. LAMBERT

IPC: H01L23/498 ,  H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L21/3205 ,  H01L23/00 ,  H01L21/32

CPC classification number: H01L23/49838 ,  H01L21/02263 ,  H01L21/28556 ,  H01L21/32 ,  H01L21/3205 ,  H01L21/4857 ,  H01L21/768 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/1205 ,  H05K1/162

Abstract: A hybrid pitch package includes a standard package pitch zone of the package having only standard package pitch sized features that is adjacent to a smaller processor pitch sized zone of the package having smaller processor pitch sized features. The package may be formed by obtaining a package having standard package pitch sized features (such as from another location or a package processing facility), forming a protective mask over a standard package pitch zone of the package that is adjacent to a smaller processor pitch sized zone on the package, and then forming smaller processor pitch sized features (such as contacts, traces and interconnects) in the smaller processor pitch sized zone at a chip fabrication processing facility. The smaller processor pitch sized features can be directly connected to (thus reducing the package connection area needed) a chip or device having processor pitch sized features (e.g., exposed contacts).