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    Data storage device with operation based on temperature difference
    11.
    发明授权
    Data storage device with operation based on temperature difference 有权

    公开(公告)号：US10276252B2

    公开(公告)日：2019-04-30

    申请号：US15838202

    申请日：2017-12-11

    Applicant: Intel Corporation

    Inventor： Aliasgar S. Madraswala ,  Xin Guo ,  Ali Khakifirooz ,  Pranav Kalavade ,  Sagar Upadhyay

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/22 ,  G11C16/10 ,  G11C11/56

    Abstract: Embodiments of the present disclosure may relate to a memory controller that may include a memory interface and a logic circuitry component coupled with the memory interface. In some embodiments, the logic circuitry component is to program one or more NAND cells of a multi-level NAND memory array via the memory interface with a first set of data in a first pass, determine a first temperature of the multi-level NAND memory array in association with the first pass, determine a second temperature of the multi-level NAND memory array, determine a temperature difference between the second temperature and the first temperature, and perform one or more operations based at least in part on a result of the determination of the temperature difference. Other embodiments may be described and/or claimed.

    Apparatuses, systems, and methods for heating a memory device
    16.
    发明授权
    Apparatuses, systems, and methods for heating a memory device 有权

    公开(公告)号：US11625191B2

    公开(公告)日：2023-04-11

    申请号：US16779472

    申请日：2020-01-31

    Applicant: Intel Corporation

    Inventor： Arash Hazeghi ,  Pranav Kalavade ,  Rohit Shenoy ,  Krishna Parat

    IPC: G06F3/06 ,  G05B19/406

    Abstract: An apparatus and/or system is described including a memory device or a controller for the memory device to perform heating of the memory device. In embodiments, a controller is to receive a temperature of the memory device and determine that the temperature is below a threshold temperature. In embodiments, the controller activates a heater for one or more memory die to assist the memory device in moving the temperature towards the threshold temperature, to assist the memory device when reading data. In embodiments, the heater comprises a plurality of conductive channels included in the one or more memory die or other on-board heater. Other embodiments are disclosed and claimed.

    Boosted bitlines for storage cell programmed state verification in a memory array
    18.
    发明授权
    Boosted bitlines for storage cell programmed state verification in a memory array 有权

    公开(公告)号：US11056203B1

    公开(公告)日：2021-07-06

    申请号：US16788194

    申请日：2020-02-11

    Applicant: INTEL CORPORATION

    Inventor： Xiang Yang ,  Pranav Kalavade ,  Ali Khakifirooz ,  Shantanu R. Rajwade ,  Sagar Upadhyay

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C11/56

    Abstract: In one aspect of programmed state verification in accordance with the present description, the voltage levels on bitlines of non-target storage cells are each boosted by applying a non-zero offset or delta value, ΔV, to the bitlines of non-target storage cells during a precharge subinterval. A bitline verification voltage applied to a bitline of a target storage cell causes the voltage of the bitline to ramp up from the boosted ΔV value. As a result, starting from an initial value which is the higher or boosted ΔV value, the bitline voltage ramps up more quickly during the precharge subinterval to the bitline verification voltage level to improve system performance. In addition, the bitline verification voltage applied to bitlines of target storage cells during the precharge subinterval, can be at a relatively high value to maintain the accuracy of program state verification.

    Defective bit line management in connection with a memory access
    20.
    发明授权
    Defective bit line management in connection with a memory access 有权

    公开(公告)号：US10942799B1

    公开(公告)日：2021-03-09

    申请号：US16562745

    申请日：2019-09-06

    Applicant: Intel Corporation

    Inventor： Ali Khakifirooz ,  Pranav Kalavade ,  Ravi H. Motwani ,  Chang Wan Ha

    IPC: G06F11/07 ,  G11C16/34 ,  G11C7/12 ,  G11C29/44 ,  G11C16/14

    Abstract: Examples herein relate to determining a number of defective bit lines in a memory region prior to applying a program or erase voltages. If a threshold number of bit lines that pass during a program or erase verify operation is used to determine if the program or erase operation passes or fails, the determined number of defective bit lines can be used to adjust the determined number of passes or fails. In some cases, examples described herein can avoid use of extra bit lines and look-up table circuitry to use in place of defective bit lines and save silicon space and cost associated with the use of extra bit-lines. In some examples, a starting magnitude of a program voltage signal can be determined by considering a number of defective bit lines.

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