公开(公告)号：US20240049450A1

公开(公告)日：2024-02-08

申请号：US18381119

申请日：2023-10-17

Applicant: Intel Corporation

Inventor： Travis W. LAJOIE ,  Abhishek A. SHARMA ,  Van H. LE ,  Chieh-Jen KU ,  Pei-Hua WANG ,  Jack T. KAVALIEROS ,  Bernhard SELL ,  Tahir GHANI ,  Gregory GEORGE ,  Akash GARG ,  Allen B. GARDINER ,  Shem OGADHOH ,  Juan G. ALZATE VINASCO ,  Umut ARSLAN ,  Fatih HAMZAOGLU ,  Nikhil MEHTA ,  Jared STOEGER ,  Yu-Wen HUANG ,  Shu ZHOU

IPC: H10B12/00 ,  H01L27/12

CPC classification number: H10B12/315 ,  H01L27/1218 ,  H01L27/1222 ,  H01L27/1225 ,  H01L28/82 ,  H01L27/1248 ,  H01L27/1255 ,  H01L28/55 ,  H01L28/65 ,  H01L27/124 ,  H10B12/312 ,  H10B12/0335

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.

公开(公告)号：US20240006489A1

公开(公告)日：2024-01-04

申请号：US18367843

申请日：2023-09-13

Applicant: Intel Corporation

Inventor： Aaron LILAK ,  Rishabh MEHANDRU ,  Willy RACHMADY ,  Harold KENNEL ,  Tahir GHANI

IPC: H01L29/08 ,  H01L21/02 ,  H01L21/8238

CPC classification number: H01L29/0847 ,  H01L21/02356 ,  H01L21/02592 ,  H01L21/823871 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823807

Abstract: A device is disclosed. The device includes a channel, a first source-drain region adjacent a first portion of the channel, the first source-drain region including a first crystalline portion that includes a first region of metastable dopants, a second source-drain region adjacent a second portion of the channel, the second source-drain region including a second crystalline portion that includes a second region of metastable dopants. A gate conductor is on the channel.

公开(公告)号：US20230420533A1

公开(公告)日：2023-12-28

申请号：US17851960

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Wilfred GOMES ,  Anand S. MURTHY ,  Tahir GHANI ,  Sagar SUTHRAM

IPC: H01L29/423 ,  H01L27/12 ,  H01L27/092 ,  H01L23/528 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L27/1203 ,  H01L27/092 ,  H01L23/528 ,  H01L29/401 ,  H01L29/66439 ,  H01L29/66742

Abstract: Structures having AOI gates with routing across nanowires are described. In an example, an integrated circuit structure includes a stack of horizontal nanowires along a vertical direction. A gate stack is over the stack of horizontal nanowires and is surrounding a channel region of each of the horizontal nanowires, the gate stack having one or more cuts in the vertical direction.

公开(公告)号：US20230387315A1

公开(公告)日：2023-11-30

申请号：US18227233

申请日：2023-07-27

Applicant: Intel Corporation

Inventor： Abhishek A. SHARMA ,  Van H. LE ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Gilbert DEWEY

IPC: H01L29/786 ,  H01L29/423

CPC classification number: H01L29/78648 ,  H01L29/42384 ,  H01L29/78603 ,  H01L29/78672 ,  H01L29/7869 ,  H01L2029/42388

Abstract: Thin film transistors having double gates are described. In an example, an integrated circuit structure includes an insulator layer above a substrate. A first gate stack is on the insulator layer. A polycrystalline channel material layer is on the first gate stack. A second gate stack is on a first portion of the polycrystalline channel material layer, the second gate stack having a first side opposite a second side. A first conductive contact is adjacent the first side of the second gate stack, the first conductive contact on a second portion of the channel material layer. A second conductive contact is adjacent the second side of the second gate stack, the second conductive contact on a third portion of the channel material layer.

公开(公告)号：US20230343826A1

公开(公告)日：2023-10-26

申请号：US18216563

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand MURTHY ,  Anupama BOWONDER ,  Aaron BUDREVICH ,  Tahir GHANI

IPC: H01L29/08 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66636 ,  H01L21/02532 ,  H01L21/02579 ,  H01L29/66795 ,  H01L29/7851

Abstract: Embodiments of the disclosure include integrated circuit structures having source or drain dopant diffusion blocking layers. In an example, an integrated circuit structure includes a fin including silicon. A gate structure is over a channel region of the fin, the gate structure having a first side opposite a second side. A first source or drain structure is at the first side of the gate structure. A second source or drain structure is at the second side of the gate structure. The first and second source or drain structures include a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is in contact with the channel region of the fin, and the second semiconductor layer is on the first semiconductor layer. The first semiconductor layer has a greater concentration of germanium than the second semiconductor layer, and the second semiconductor layer includes boron dopant impurity atoms.

公开(公告)号：US20230317787A1

公开(公告)日：2023-10-05

申请号：US17709374

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Mauro J. KOBRINSKY ,  Mohit K. HARAN ,  Marni NABORS ,  Tahir GHANI ,  Charles H. WALLACE ,  Allen B. GARDINER ,  Sukru YEMENICIOGLU

IPC: H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0673 ,  H01L27/0886

Abstract: Integrated circuit structures having backside gate tie-down are described. In an example, a structure includes a first vertical stack of horizontal nanowires over a first sub-fin, and a second vertical stack of horizontal nanowires over a second sub-fin, the second vertical stack of horizontal nanowires spaced apart from and parallel with the first vertical stack of horizontal nanowires. A gate structure includes a first gate structure portion over the first vertical stack of horizontal nanowires, wherein the first gate structure extends along an entirety of the first sub-fin. A second gate structure portion is over the second vertical stack of horizontal nanowires, wherein the second gate structure does not extend along an entirety of the second sub-fin. A gate cut is between the first gate structure portion and the second gate structure portion.

公开(公告)号：US20230317786A1

公开(公告)日：2023-10-05

申请号：US17700215

申请日：2022-03-21

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Cory WEBER ,  Varun MISHRA ,  Tahir GHANI ,  Pratik PATEL ,  Wonil CHUNG ,  Mohammad HASAN

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/0673 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439

Abstract: Gate-all-around integrated circuit structures having necked features, and methods of fabricating gate-all-around integrated circuit structures having necked features, are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires. Each nanowire of the vertical stack of horizontal nanowires has a channel portion with a first vertical thickness and has end portions with a second vertical thickness greater than the first vertical thickness. A gate stack is surrounding the channel portion of each nanowire of the vertical stack of horizontal nanowires.

公开(公告)号：US20230275157A1

公开(公告)日：2023-08-31

申请号：US18143549

申请日：2023-05-04

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand S. MURTHY ,  Tahir GHANI ,  Anupama BOWONDER

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7853 ,  H01L29/66818 ,  H01L29/165 ,  H01L29/7851

Abstract: Fin smoothing, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure, the protruding fin portion having substantially vertical sidewalls. The semiconductor fin further includes a sub-fin portion within an opening in the isolation structure, the sub-fin portion having a different semiconductor material than the protruding fin portion. The sub-fin portion has a width greater than or less than a width of the protruding portion where the sub-fin portion meets the protruding portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region at a first side of the gate stack, and a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.

公开(公告)号：US20230197780A1

公开(公告)日：2023-06-22

申请号：US17557932

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Tahir GHANI ,  Charles H. WALLACE

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/66742

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a fin with a first end and a second end. In an embodiment, a first dielectric covers the first end of the fin, and a second dielectric covers the second end of the fin. In an embodiment, a gate structure is over the first end of the fin, where the gate structure is on a top surface of the fin and a top surface of the first dielectric.

公开(公告)号：US20230093657A1

公开(公告)日：2023-03-23

申请号：US17482228

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Mohit K. HARAN ,  Mohammad HASAN ,  Tahir GHANI ,  Anand S. MURTHY

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

Abstract: Integrated circuit structures having a dielectric gate wall and a dielectric gate plug, and methods of fabricating integrated circuit structures having a dielectric gate wall and a dielectric gate plug, are described. For example, an integrated circuit structure includes a sub-fin having a portion protruding above a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is over the protruding portion of the sub-fin, over the STI structure, and surrounding the horizontally stacked nanowires. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate wall is laterally spaced apart from the sub-fin and the plurality of horizontally stacked nanowires, the dielectric gate wall on the STI structure. A dielectric gate plug is on the dielectric gate wall.