公开(公告)号：US20170109286A1

公开(公告)日：2017-04-20

申请号：US15393577

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Robert G. Blankenship ,  Bahaa Fahim ,  Robert H. Beers ,  Yen-Cheng Liu ,  Vedaraman Geetha ,  Herbert H. Hum ,  Jeff Willey

IPC: G06F12/0831 ,  G06F12/0808

CPC classification number: G06F13/22 ,  G06F1/3287 ,  G06F8/71 ,  G06F8/73 ,  G06F8/77 ,  G06F9/30145 ,  G06F9/44505 ,  G06F9/466 ,  G06F11/1004 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4273 ,  G06F13/4282 ,  G06F13/4286 ,  G06F13/4291 ,  G06F2212/1016 ,  G06F2212/2542 ,  G06F2212/622 ,  H04L9/0662 ,  H04L12/4641 ,  H04L45/74 ,  H04L49/15 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/40 ,  Y02D10/44 ,  Y02D30/30

Abstract: A request is received that is to reference a first agent and to request a particular line of memory to be cached in an exclusive state. A snoop request is sent intended for one or more other agents. A snoop response is received that is to reference a second agent, the snoop response to include a writeback to memory of a modified cache line that is to correspond to the particular line of memory. A complete is sent to be addressed to the first agent, wherein the complete is to include data of the particular line of memory based on the writeback.

公开(公告)号：US09606925B2

公开(公告)日：2017-03-28

申请号：US14669248

申请日：2015-03-26

Applicant: Intel Corporation

Inventor： Bahaa Fahim ,  Yen-Cheng Liu ,  Vedaraman Geetha ,  Jeffrey D. Chamberlain ,  Min Huang

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/0855 ,  G06F12/0817 ,  G06F12/0831 ,  G06F2212/27 ,  G06F2212/621 ,  Y02D10/13

Abstract: In one embodiment, a processor includes a caching home agent (CHA) coupled to a core and a cache memory and includes a cache controller having a cache pipeline and a home agent having a home agent pipeline. The CHA may: receive, in the home agent pipeline, information from an external agent responsive to a miss for data in the cache memory; issue a global ordering signal from the home agent pipeline to a requester of the data to inform the requester of receipt of the data; and report issuance of the global ordering signal to the cache pipeline, to prevent the cache pipeline from issuance of a global ordering signal to the requester. Other embodiments are described and claimed.

公开(公告)号：US09471494B2

公开(公告)日：2016-10-18

申请号：US14137432

申请日：2013-12-20

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  Neil M. Schaper ,  Joseph Nuzman ,  Larisa Novakovsky ,  Yen-Cheng Liu ,  Gilbert Neiger ,  Raj K. Ramanujan

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0804 ,  G06F12/0815 ,  G06F12/0831 ,  G06F2212/1032 ,  G06F2212/222

Abstract: An apparatus and method are described for performing a cache line write back operation. For example, one embodiment of a method comprises: initiating a cache line write back operation directed to a particular linear address; determining if a dirty cache line identified by the linear address exists at any cache of a cache hierarchy comprised of a plurality of cache levels; writing back the dirty cache line to memory if the dirty cache line exists in one of the caches; and responsively maintaining or placing the dirty cache line in an exclusive state in at least a first cache of the hierarchy.

Abstract translation: 描述了用于执行高速缓存行回写操作的装置和方法。 例如，方法的一个实施例包括：发起针对特定线性地址的高速缓存行回写操作; 确定由线性地址识别的脏高速缓存行是否存在于由多个高速缓存级别组成的高速缓存层级的任何高速缓存上; 如果脏缓存行存在于其中一个缓存中，则将脏缓存行写回内存; 以及响应地将所述脏高速缓存行维持或置于所述层次结构的至少第一高速缓存中的排他状态。

公开(公告)号：US09436605B2

公开(公告)日：2016-09-06

申请号：US14136131

申请日：2013-12-20

Applicant: Intel Corporation

Inventor： Jeffrey D. Chamberlain ,  Vedaraman Geetha ,  Robert G. Blankenship ,  Yen-Cheng Liu ,  Adrian C. Moga ,  Herbert H. Hum ,  Sailesh Kottapalli

IPC: G06F12/08

CPC classification number: G06F12/0817 ,  G06F12/0815

Abstract: An apparatus and method for reducing or eliminating writeback operations. For example, one embodiment of a method comprises: detecting a first operation associated with a cache line at a first requestor cache; detecting that the cache line exists in a first cache in a modified (M) state; forwarding the cache line from the first cache to the first requestor cache and storing the cache line in the first requestor cache in a second modified (M′) state; detecting a second operation associated with the cache line at a second requestor; responsively forwarding the cache line from the first requestor cache to the second requestor cache and storing the cache line in the second requestor cache in an owned (O) state if the cache line has not been modified in the first requestor cache; and setting the cache line to a shared (S) state in the first requestor cache.

Abstract translation: 一种用于减少或消除写回操作的设备和方法。 例如，方法的一个实施例包括：在第一请求者高速缓存处检测与高速缓存行相关联的第一操作; 检测到所述高速缓存行存在于修改（M）状态的第一高速缓存中; 将所述高速缓存行从所述第一高速缓存转发到所述第一请求者高速缓存，并且以第二修改（M'）状态将所述高速缓存行存储在所述第一请求程序高速缓存中; 在第二请求者处检测与所述高速缓存线相关联的第二操作; 响应地将所述高速缓存行从所述第一请求者缓存转发到所述第二请求器高速缓存，并且如果所述高速缓存行尚未在所述第一请求者高速缓存中被修改则将所述高速缓存行存储在所述第二请求程序高速缓存中; 以及将所述高速缓存行设置为所述第一请求者缓存中的共享（S）状态。

公开(公告)号：US09405687B2

公开(公告)日：2016-08-02

申请号：US14070864

申请日：2013-11-04

Applicant: Intel Corporation

Inventor： Bahaa Fahim ,  Samuel D. Strom ,  Vedaraman Geetha ,  Robert G. Blankenship ,  Yen-Cheng Liu ,  Krishnakumar Ganapathy ,  Cesar Maldonado

IPC: G06F12/08

CPC classification number: G06F12/0813 ,  G06F12/0831 ,  G06F12/0884 ,  G06F2212/2542 ,  Y02D10/13

Abstract: In an embodiment, a processor includes one or more cores, and a distributed caching home agent (including portions associated with each core). Each portion includes a cache controller to receive a read request for data and, responsive to the data not being present in a cache memory associated with the cache controller, to issue a memory request to a memory controller to request the data in parallel with communication of the memory request to a home agent, where the home agent is to receive the memory request from the cache controller and to reserve an entry for the memory request. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括一个或多个核心和分布式缓存归属代理（包括与每个核心相关联的部分）。 每个部分包括高速缓存控制器，用于接收对数据的读取请求，并且响应于不存在于与高速缓存控制器相关联的高速缓冲存储器中的数据，向存储器控制器发出存储器请求以与 对归属代理的存储器请求，其中归属代理将从高速缓存控制器接收存储器请求并且为存储器请求保留条目。 描述和要求保护其他实施例。

公开(公告)号：US20150095580A1

公开(公告)日：2015-04-02

申请号：US14040375

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Yen-Cheng Liu ,  Bahaa Fahim ,  Erik G. Hallnor ,  Jeffrey D. Chamberlain ,  Stephen R. Van Doren ,  Antonio Juan

IPC: G06F12/08

Abstract: A processor includes a cache-side address monitor unit corresponding to a first cache portion of a distributed cache that has a total number of cache-side address monitor storage locations less than a total number of logical processors of the processor. Each cache-side address monitor storage location is to store an address to be monitored. A core-side address monitor unit corresponds to a first core and has a same number of core-side address monitor storage locations as a number of logical processors of the first core. Each core-side address monitor storage location is to store an address, and a monitor state for a different corresponding logical processor of the first core. A cache-side address monitor storage overflow unit corresponds to the first cache portion, and is to enforce an address monitor storage overflow policy when no unused cache-side address monitor storage location is available to store an address to be monitored.

Abstract translation: 处理器包括对应于分布式高速缓存的第一高速缓存部分的高速缓存器侧地址监视器单元，其具有小于处理器的逻辑处理器总数的高速缓存器侧地址监视器存储位置的总数。 每个缓存侧地址监视器存储位置是存储要监视的地址。 核心侧地址监视器单元对应于第一核心，并且具有与第一核心的多个逻辑处理器相同数量的核心侧地址监视器存储位置。 每个核心侧地址监视器存储位置用于存储第一核心的不同对应逻辑处理器的地址和监视状态。 高速缓存侧地址监视器存储溢出单元对应于第一高速缓存部分，并且当没有未使用的高速缓存侧地址监视器存储位置可用于存储要监视的地址时，强制执行地址监视器存储溢出策略。

公开(公告)号：US08700933B2

公开(公告)日：2014-04-15

申请号：US13787085

申请日：2013-03-06

Applicant: Intel Corporation

Inventor： Yen-Cheng Liu ,  P Keong Or ,  Krishnakanth Sistla ,  Ganapati Srinivasa

IPC: G06F1/26 ,  G06F1/22

CPC classification number: G06F1/3243 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F12/0811 ,  G06F15/80 ,  G06F2212/283 ,  G11C7/1072 ,  G11C7/1075 ,  Y02D10/16

Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.

Abstract translation: 公开了一种监视架构事件的方法和装置。 架构事件通过推送总线机制链接在一起，每个架构事件都具有指定的时隙。 在每个核心中至少有一个分支的推送总线。 推送总线的每个分支可以监视一个核心与所有的架构事件。 然后将通过推送总线从事件收集的所有数据发送到电源控制单元。

公开(公告)号：US12197357B2

公开(公告)日：2025-01-14

申请号：US17556853

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/22 ,  G06F1/3287 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30 ,  G06F9/445 ,  G06F9/46 ,  G06F11/10 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F13/40 ,  G06F13/42 ,  H04L9/06 ,  H04L49/15 ,  G06F8/73 ,  H04L12/46 ,  H04L45/74

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

公开(公告)号：US20240012772A1

公开(公告)日：2024-01-11

申请号：US18347236

申请日：2023-07-05

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/22 ,  H04L49/15 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F13/42 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30 ,  G06F12/0806 ,  G06F9/46 ,  G06F13/40 ,  G06F9/445 ,  G06F1/3287 ,  G06F11/10 ,  H04L9/06 ,  G06F12/0808

CPC classification number: G06F13/22 ,  H04L49/15 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F13/4286 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30145 ,  G06F13/4221 ,  G06F12/0806 ,  G06F12/0833 ,  G06F9/466 ,  G06F13/4022 ,  G06F9/44505 ,  G06F13/4282 ,  G06F1/3287 ,  G06F13/4068 ,  G06F11/1004 ,  G06F13/4291 ,  H04L9/0662 ,  G06F12/0808 ,  H04L45/74

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

公开(公告)号：US20230091205A1

公开(公告)日：2023-03-23

申请号：US17479582

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Adrian Moga ,  Ugonna Echeruo ,  Eduard Roytman ,  Krishnakanth Sistla ,  Joseph Nuzman ,  Brinda Ganesh ,  Meenakshisundaram Chinthamani ,  Yen-Cheng Liu ,  Sai Prashanth Muralidhara ,  Vivek Kozhikkottu ,  Hanna Alam ,  Narasimha Sridhar Srirangam

IPC: G06F12/0862 ,  G06F13/28

Abstract: Methods and apparatus relating to memory side prefetch architecture for improved memory bandwidth are described. In an embodiment, logic circuitry transmits a Direct Memory Controller Prefetch (DMCP) request to cause a prefetch of data from memory. A memory controller receives the DMCP request and issues a plurality of read operations to the memory in response to the DMCP request. Data read from the memory is stored in a storage structure in response to the plurality of read operations. Other embodiments are also disclosed and claimed.