公开(公告)号：US08963117B2

公开(公告)日：2015-02-24

申请号：US14018719

申请日：2013-09-05

Applicant: Intermolecular Inc.

Inventor： Pragati Kumar ,  Tony P. Chiang ,  Prashant B Phatak ,  Yun Wang

IPC: H01L47/00 ,  H01L45/00 ,  G11C13/00 ,  H01L27/24

CPC classification number: H01L45/146 ,  G11C13/0002 ,  G11C2013/0083 ,  G11C2213/51 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1625 ,  H01L45/1641

Abstract: This disclosure provides a nonvolatile memory device and related methods of manufacture and operation. The device may include one or more resistive random access memory (ReRAM) approaches to provide a memory device with more predictable operation. In particular, the forming voltage required by particular designs may be reduced through the use of a barrier layer, a reverse polarity forming voltage pulse, a forming voltage pulse where electrons are injected from a lower work function electrode, or an anneal in a reducing environment. One or more of these techniques may be applied, depending on the desired application and results.

公开(公告)号：US20140318450A1

公开(公告)日：2014-10-30

申请号：US14326289

申请日：2014-07-08

Applicant: Intermolecular, Inc.

Inventor： Richard R. Endo ,  Tony P. Chiang ,  James Tsung

IPC: C23C16/52

CPC classification number: C23C16/52 ,  C23C14/042 ,  C23C14/54 ,  C23C14/568 ,  H01L21/67184 ,  H01L21/67207 ,  H01L21/67236 ,  H01L21/67276 ,  H01L21/67745 ,  H01L21/67769

Abstract: A system for processing a semiconductor substrate is provided. The system includes a mainframe having a plurality of modules attached thereto. The modules include processing modules, storage modules, and transport mechanisms. The processing modules may include combinatorial processing modules and conventional processing modules, such as surface preparation, thermal treatment, etch and deposition modules. In one embodiment, at least one of the modules stores multiple masks. The multiple masks enable in-situ variation of spatial location and geometry across a sequence of processes and/or multiple layers of a substrate to be processed in another one of the modules. A method for processing a substrate is also provided.

Abstract translation: 提供了一种用于处理半导体衬底的系统。 该系统包括具有附接到其上的多个模块的主机。 模块包括处理模块，存储模块和传输机制。 处理模块可以包括组合处理模块和常规处理模块，例如表面处理，热处理，蚀刻和沉积模块。 在一个实施例中，至少一个模块存储多个掩模。 多个掩模使得能够在另一个模块中要处理的衬底的一系列工艺和/或多个层的空间位置和几何形状的原位变化。 还提供了一种处理基板的方法。

公开(公告)号：US20140269004A1

公开(公告)日：2014-09-18

申请号：US14137893

申请日：2013-12-20

Applicant: Intermolecular, Inc.

Inventor： Dipankar Pramanik ,  Tony P. Chiang

IPC: G11C13/00 ,  H01L45/00

CPC classification number: H01L27/2418 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/15 ,  G11C2213/71 ,  G11C2213/77 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/283 ,  H01L21/324 ,  H01L22/12 ,  H01L22/34 ,  H01L27/24 ,  H01L27/2463 ,  H01L28/60 ,  H01L45/00 ,  H01L45/04 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/14 ,  H01L45/144 ,  H01L45/145 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1641 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Programming a resistive memory structure at a temperature well above the operating temperature can create a defect distribution with higher stability, leading to a potential improvement of the retention time. The programming temperature can be up to 100 C above the operating temperature. The memory chip can include embedded heaters in the chip package, allowing for heating the memory cells before the programming operations.

Abstract translation: 在远高于工作温度的温度下对阻性存储器结构进行编程可以产生具有更高稳定性的缺陷分布，导致保留时间的潜在改善。 编程温度可高达工作温度100℃。 存储器芯片可以包括芯片封装中的嵌入式加热器，从而允许在编程操作之前加热存储器单元。

公开(公告)号：US20140183439A1

公开(公告)日：2014-07-03

申请号：US13728860

申请日：2012-12-27

Applicant: INTERMOLECULAR, INC.

Inventor： Imran Hashim ,  Venkat Ananthan ,  Tony P. Chiang ,  Prashant B. Phatak

IPC: H01L29/872 ,  H01L29/66 ,  H01L27/24

CPC classification number: H01L27/2418 ,  H01L27/2409 ,  H01L29/872 ,  H01L45/10

Abstract: Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a high leakage dielectric layer sandwiched between two lower leakage dielectric layers. The low leakage layers can function to restrict the current flow across the selector device at low voltages. The high leakage dielectric layer can function to enhance the current flow across the selector device at high voltages.

Abstract translation: 可适用于存储器件应用的选择器器件可在低电压下具有低漏电流，以减少非选定器件的漏电流路径，以及高电压下的高泄漏电流，以最大限度地减少器件切换期间的电压降。 在一些实施例中，选择器装置可以包括第一电极，三层电介质层和第二电极。 三层电介质层可以包括夹在两个较低的漏电介质层之间的高泄漏电介质层。 低泄漏层可以起到限制低电压下选择器装置的电流的作用。 高泄漏电介质层可以用于在高电压下增强选择器装置上的电流。

公开(公告)号：US20140175354A1

公开(公告)日：2014-06-26

申请号：US13721549

申请日：2012-12-20

Applicant: INTERMOLECULAR INC. ,  KABUSHIKI KAISHA TOSHIBA ,  SANDISK 3D LLC

Inventor： Yun Wang ,  Tony P. Chiang ,  Tim Minvielle ,  Takeshi Yamaguchi

IPC: H01L45/00

CPC classification number: H01L45/145 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616

Abstract: Provided are methods of forming nonvolatile memory elements using atomic layer deposition techniques, in which at least two different layers of a memory element are deposited sequentially and without breaking vacuum in a deposition chamber. This approach may be used to prevent oxidation of various materials used for electrodes without a need for separate oxygen barrier layers. A combination of signal lines and resistive switching layers may be used to cap the electrodes and to minimize their oxidation. As such, fewer layers are needed in a memory element. Furthermore, atomic layer deposition allows more precise control of electrode thicknesses. In some embodiments, a thickness of an electrode may be less than 50 Angstroms. Overall, atomic layer deposition of electrodes and resistive switching layers lead to smaller thicknesses of entire memory elements making them more suitable for low aspect ratio features of advanced nodes.

Abstract translation: 提供了使用原子层沉积技术形成非易失性存储元件的方法，其中存储元件的至少两个不同层顺次沉积并且在沉积室中不破坏真空。 该方法可以用于防止用于电极的各种材料的氧化，而不需要单独的氧阻隔层。 可以使用信号线和电阻开关层的组合来封盖电极并使其氧化最小化。 因此，存储元件中需要更少的层。 此外，原子层沉积允许更精确地控制电极厚度。 在一些实施例中，电极的厚度可以小于50埃。 总的来说，电极和电阻开关层的原子层沉积导致整个存储元件的较小厚度，使得它们更适合于高级节点的低纵横比特征。

公开(公告)号：US20140166107A1

公开(公告)日：2014-06-19

申请号：US13714274

申请日：2012-12-13

Applicant: INTERMOLECULAR, INC.

Inventor： Mankoo Lee ,  Sergey Barabash ,  Tony P. Chiang ,  Dipankar Pramanik

IPC: H01L31/0264 ,  H01L31/18

CPC classification number: H01L31/056 ,  H01L31/0322 ,  H01L31/03923 ,  H01L31/0749 ,  Y02E10/52 ,  Y02E10/541

Abstract: Methods for improving the efficiency of solar cells are disclosed. A solar cell consistent with the present disclosure includes a back contact metal layer disposed on a substrate. The solar cell also includes an electron reflector material(s) layer formed on the back contact metal layer and an absorber material(s) layer disposed on the electron reflector material(s) layer. In addition, the solar cell includes a buffer material(s) layer formed on the absorber material(s) layer wherein the electron reflector material(s) layer, absorber material(s) layer, and buffer material(s) layer form a pn junction within the solar cell. Furthermore, a TCO material(s) layer is formed on the buffer material(s) layer. In addition, the front contact layer is formed on the TCO material(s) layer.

Abstract translation: 公开了提高太阳能电池效率的方法。 符合本公开的太阳能电池包括设置在基板上的背接触金属层。 太阳能电池还包括形成在背接触金属层上的电子反射器材料层和设置在电子反射器材料层上的吸收体材料层。 此外，太阳能电池包括形成在吸收材料层上的缓冲材料层，其中电子反射器材料层，吸收材料层和缓冲材料层形成pn 太阳能电池内的接头。 此外，在缓冲材料层上形成TCO材料层。 此外，前接触层形成在TCO材料层上。

公开(公告)号：US20140117303A1

公开(公告)日：2014-05-01

申请号：US13722314

申请日：2012-12-20

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang ,  Tony P. Chiang ,  Imran Hashim ,  Tim Minvielle ,  Dipankar Pramanik ,  Takeshi Yamaguchi

IPC: H01L45/00

CPC classification number: H01L45/1608 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/56 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

Abstract: Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from alloys of transition metals. Some examples of such alloys include chromium containing alloys that may also include nickel, aluminum, and/or silicon. Other examples include tantalum and/or titanium containing alloys that may also include a combination of silicon and carbon or a combination of aluminum and nitrogen. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature processing. In some embodiments, the breakdown voltage of a current limiting layer is at least about 8V. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layers while maintaining their performance.

公开(公告)号：US20140077336A1

公开(公告)日：2014-03-20

申请号：US13737125

申请日：2013-01-09

Applicant: INTERMOLECULAR INC.

Inventor： Tony P. Chiang ,  Wim Y. Deweerd ,  Sandra G. Malhotra

IPC: H01L29/92

CPC classification number: H01L29/92 ,  H01L27/10852 ,  H01L28/40

Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high-k phase of a subsequently deposited dielectric layer. The high-k dielectric layer includes a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.

Abstract translation: 用于形成具有低漏电流的DRAM MIM电容器堆叠的方法涉及使用用作促进随后沉积的介电层的高k相的模板的第一电极。 高k电介质层包括可在随后的退火处理后结晶的掺杂材料。 在电介质层上形成无定形阻挡层。 选择阻挡层的厚度使得在随后的退火处理之后阻挡层保持无定形。 在阻挡层上形成与阻挡层相容的第二电极层。

公开(公告)号：US20140065819A1

公开(公告)日：2014-03-06

申请号：US13672621

申请日：2012-11-08

Applicant: INTERMOLECULAR, INC.

Inventor： Khaled Ahmed ,  Tony P. Chiang

IPC: H01L21/3205

CPC classification number: H01L21/28556 ,  H01L21/2255 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/2855 ,  H01L29/665

Abstract: Methods for improving contact resistance, for example, to a semiconductor region such as a source or a drain region, are disclosed. The methods can include depositing a layer on a substrate, wherein the layer can include a first element to form a silicide with the substrate and a second element to lower a contact resistance between the silicide and the substrate. The second element can include a dopant, which can enhance trap assisted tunneling or lower the Schottky barrier height between the silicide layer and the substrate.

Abstract translation: 公开了用于提高接触电阻的方法，例如提供到诸如源极或漏极区域的半导体区域。 所述方法可以包括在衬底上沉积层，其中所述层可以包括与衬底形成硅化物的第一元件和第二元件以降低硅化物和衬底之间的接触电阻。 第二元素可以包括掺杂剂，其可以增强陷阱辅助隧穿或降低硅化物层和衬底之间的肖特基势垒高度。

公开(公告)号：US08652923B2

公开(公告)日：2014-02-18

申请号：US13829194

申请日：2013-03-14

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang ,  Tony P. Chiang ,  Imran Hashim

IPC: H01L21/20

CPC classification number: H01L45/1608 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/065 ,  H01L45/08 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625

Abstract: Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.

Abstract translation: 本发明的实施例一般涉及具有设置在至少一个电极和形成在非易失性存储器件中的可变电阻层之间的界面层结构的电阻式开关非易失性存储器件及其形成方法。 通常，电阻式开关存储器元件可以形成为可用于各种电子设备（例如数码相机，移动电话，手持式计算机和音乐播放器）的大容量非易失性存储器集成电路的一部分。 在电阻式开关非易失性存储器件的一种结构中，界面层结构包括钝化区域，界面耦合区域和/或可变电阻层接口区域，其被配置为调整非易失性存储器件的性能，例如降低形成 器件的开关电流并降低器件的成型电压，并降低从一个成形器件到另一个器件的性能变化。