公开(公告)号：US09177950B2

公开(公告)日：2015-11-03

申请号：US14566751

申请日：2014-12-11

Applicant: Infineon Technologies AG

Inventor： Andre Schmenn ,  Damian Sojka ,  Carsten Ahrens

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/02 ,  H01L29/66 ,  H01L29/868 ,  H01L21/22 ,  H01L21/265

CPC classification number: H01L27/0255 ,  H01L21/22 ,  H01L21/265 ,  H01L29/66121 ,  H01L29/868

Abstract: Described herein is a protective structure. The protective structure includes a semiconductor substrate, a first diode disposed at least one of in or on the semiconductor substrate and a diode arrangement disposed at least one of in or on the semiconductor substrate. The diode arrangement includes a stack of a second diode and a transient voltage suppressor (TVS) diode connected in series with the second diode. The diode arrangement is in parallel with the first diode.

Abstract translation: 这里描述的是保护结构。 保护结构包括半导体衬底，设置在半导体衬底中或半导体衬底中的至少一个上的第一二极管和设置在半导体衬底中或半导体衬底中的至少之一上的二极管布置。 二极管装置包括与第二二极管串联连接的第二二极管和瞬态电压抑制器（TVS）二极管的堆叠。 二极管布置与第一二极管并联。

公开(公告)号：US20150279833A1

公开(公告)日：2015-10-01

申请号：US14225138

申请日：2014-03-25

Applicant: Infineon Technologies AG

Inventor： Josef Dietl ,  Andre Schmenn ,  Damian Sojka

IPC: H01L27/02 ,  H01L23/495

CPC classification number: H01L27/0255 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49568 ,  H01L23/49575 ,  H01L2224/16245 ,  H01L2224/45144 ,  H01L2224/48111 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/73257 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/4554

Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a die paddle and a protection device disposed over the die paddle. The protection device includes a first heat generating zone disposed in a substrate. The first heat generating zone is disposed at a first side facing the die paddle. A solder layer at the first heat generating zone joins the protection device with the die paddle.

Abstract translation: 根据本发明的一个实施例，一种半导体封装包括裸片和设置在裸片上的保护装置。 保护装置包括设置在基板中的第一发热区域。 第一发热区设置在面对模板的第一侧。 第一发热区的焊料层将保护装置与管芯焊盘连接。

公开(公告)号：US20150221523A1

公开(公告)日：2015-08-06

申请号：US14598288

申请日：2015-01-16

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Andre Schmenn ,  Damian Sojka ,  Isabella Goetz ,  Gudrun Stranzl ,  Sebastian Werner ,  Thomas Fischer ,  Carsten Ahrens ,  Edward Fuergut

IPC: H01L21/3213 ,  H01L21/283 ,  H01L27/02 ,  H01L21/306 ,  H01L23/498 ,  H01L21/56 ,  H01L21/304

CPC classification number: H01L21/561 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/49838 ,  H01L27/0248 ,  H01L27/0255 ,  H01L29/861 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/00

Abstract: An arrangement is provided. The arrangement may include: a substrate having a front side and a back side, a die region within the substrate, a multi-purpose layer defining a back side of the die region, and an etch stop layer disposed over the multi-purpose layer between the multi-purpose layer and the back side of the substrate. The multi-purpose layer may be formed of an ohmic material, and the etch stop layer may be of a first conductivity type of a first doping concentration.

Abstract translation: 提供了一种安排。 该布置可以包括：具有前侧和后侧的基板，基板内的管芯区域，限定管芯区域的背面的多用途层以及设置在多用途层之间的蚀刻停止层， 多用途层和背面。 多用途层可以由欧姆材料形成，并且蚀刻停止层可以是第一掺杂浓度的第一导电类型。

公开(公告)号：US08951879B2

公开(公告)日：2015-02-10

申请号：US14260301

申请日：2014-04-24

Applicant: Infineon Technologies AG

Inventor： Andre Schmenn ,  Damian Sojka ,  Carsten Ahrens

IPC: H01L21/331 ,  H01L29/66 ,  H01L21/265 ,  H01L21/22

CPC classification number: H01L27/0255 ,  H01L21/22 ,  H01L21/265 ,  H01L29/66121 ,  H01L29/868

Abstract: A method for producing a protective structure may include: providing a semiconductor base substrate with a doping of a first conductivity type; producing a first epitaxial layer on the substrate; implanting a dopant of a second conductivity type in a delimited implantation region of the first epitaxial layer; applying a second epitaxial layer with a doping of the second conductivity type on the first epitaxial layer; forming an insulation zone in the second epitaxial layer, such that the second epitaxial layer is subdivided into first and second regions; producing a first dopant zone with a doping of the first conductivity type in the first region above the implantation region; producing a second dopant zone with a doping of the second conductivity type in the second region; outdiffusing the dopant from the implantation region to form a buried layer at the junction between the first epitaxial layer and the first region.

Abstract translation: 制造保护结构的方法可以包括：提供具有第一导电类型的掺杂的半导体基底衬底; 在衬底上产生第一外延层; 在所述第一外延层的界定的注入区域中注入第二导电类型的掺杂剂; 在所述第一外延层上施加掺杂所述第二导电类型的第二外延层; 在所述第二外延层中形成绝缘区，使得所述第二外延层被细分成第一和第二区域; 在注入区域上方的第一区域中产生掺杂第一导电类型的第一掺杂区; 在所述第二区域中产生掺杂所述第二导电类型的第二掺杂区; 从注入区域向外扩散掺杂剂以在第一外延层和第一区域之间的结处形成掩埋层。

公开(公告)号：US12218084B2

公开(公告)日：2025-02-04

申请号：US17702342

申请日：2022-03-23

Applicant: Infineon Technologies AG

Inventor： Andre Schmenn ,  Isabella Goetz ,  Egle Tylaite

IPC: H01L23/62 ,  H01L27/02

Abstract: An overvoltage protection device includes a semiconductor body including a substrate region disposed beneath an upper surface of the semiconductor body, first and second contact pads disposed over the upper surface of the semiconductor body, a trenched connector formed in the semiconductor body, a vertical voltage blocking device formed in the semiconductor body, wherein the trenched connector includes a trench that is formed in the upper surface of the semiconductor body and extends to the substrate region, and a metal electrode disposed within the trench, wherein the metal electrode forms an electrically conductive connection between the first contact pad and the substrate region, and wherein the voltage blocking device is connected between the second contact pad and the substrate region.

公开(公告)号：US20240186220A1

公开(公告)日：2024-06-06

申请号：US18442671

申请日：2024-02-15

Applicant: Infineon Technologies AG

Inventor： Andre Schmenn ,  Klaus Diefenbeck ,  Joost Adriaan Willemen

IPC: H01L23/482 ,  H01L21/56 ,  H01L21/822 ,  H01L27/02

CPC classification number: H01L23/4825 ,  H01L21/822 ,  H01L27/0292 ,  H01L21/56 ,  H01L27/0255

Abstract: An electrostatic discharge protection circuit includes: a first electrostatic discharge protection device structure; a first contact pad above the first electrostatic discharge protection device structure in a cross-sectional view; and below the first electrostatic discharge protection device structure in the cross-sectional view, a metal connection coupling the first electrostatic discharge protection device structure to a second contact pad remote from the first contact pad, wherein the metal connection in the cross-sectional view only partially overlaps the first electrostatic discharge protection device structure.

公开(公告)号：US20230163123A1

公开(公告)日：2023-05-25

申请号：US18100043

申请日：2023-01-23

Applicant: Infineon Technologies AG

Inventor： Vadim Valentinovic Vendt ,  Joost Willemen ,  Andre Schmenn ,  Damian Sojka

IPC: H01L27/06 ,  H01L27/02 ,  H01L29/861 ,  H01L29/66

CPC classification number: H01L27/067 ,  H01L27/0262 ,  H01L29/861 ,  H01L29/6609 ,  H01L29/7404

Abstract: A method of forming a semiconductor device includes forming a first vertical protection device comprising a thyristor in a substrate, forming a first lateral trigger element for triggering the first vertical protection device in the substrate, and forming an electrical path in the substrate to electrically couple the first lateral trigger element with the first vertical protection device.

公开(公告)号：US20220165646A1

公开(公告)日：2022-05-26

申请号：US17532446

申请日：2021-11-22

Applicant: Infineon Technologies AG

Inventor： Andre Schmenn ,  Klaus Diefenbeck ,  Joost Adriaan Willemen

IPC: H01L23/482 ,  H01L27/02 ,  H01L21/822

Abstract: In a method for manufacturing an electrostatic discharge protection circuit, an electrostatic discharge device structure is formed during a front side processing of a semiconductor substrate in a first area. Contact pads are formed on the front side on the electrostatic discharge device structure and in a second area. During back side processing of the semiconductor substrate, a metal connection between the first electrostatic discharge device structure and the second area is formed.

公开(公告)号：US20180108648A1

公开(公告)日：2018-04-19

申请号：US15787124

申请日：2017-10-18

Applicant: Infineon Technologies AG

Inventor： Vadim Valentinovic Vendt ,  Stefan Pompl ,  Andre Schmenn ,  Joost Willemen

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/74

Abstract: According an embodiment, an electrostatic discharge protection structure includes: a semiconductor layer doped with a dopant of a first doping type, a first well region extending from a surface of the semiconductor layer into the semiconductor layer, wherein the first well region is doped with a dopant of a second doping type opposite the first doping type; a second well region next to the first well region and extending from the surface of the semiconductor layer into the semiconductor layer, wherein the second well region is doped with a dopant of the first doping type; an isolation structure extending from the surface of the semiconductor layer into the semiconductor layer with a depth similar to the depth of at least one of the first well region or the second well region, wherein the isolation structure is arranged laterally adjacent to the first well region and the second well region.

公开(公告)号：US09524940B2

公开(公告)日：2016-12-20

申请号：US15003820

申请日：2016-01-22

Applicant: Infineon Technologies AG

Inventor： Thomas Fischer ,  Carsten Ahrens ,  Damian Sojka ,  Andre Schmenn

IPC: H01L21/44 ,  H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L21/784 ,  H01L21/288 ,  H01L21/78 ,  H01L23/495 ,  H01L23/482

CPC classification number: H01L27/0248 ,  H01L21/288 ,  H01L21/7685 ,  H01L21/78 ,  H01L21/784 ,  H01L23/4827 ,  H01L23/495 ,  H01L23/522 ,  H01L23/544 ,  H01L23/562 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/94 ,  H01L24/98 ,  H01L2223/5446 ,  H01L2224/04026 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/2746 ,  H01L2224/2747 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/2916 ,  H01L2224/29164 ,  H01L2224/29166 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/10337 ,  H01L2924/1037 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2224/27 ,  H01L2924/0781 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: According to various embodiments, a method for manufacturing a semiconductor device may include providing a semiconductor workpiece including a device region at a first side of the semiconductor workpiece, wherein a mechanical stability of the semiconductor workpiece is insufficient to resist at least one back end process without damage, and depositing at least one conductive layer over a second side of the semiconductor workpiece opposite the first side of the semiconductor workpiece, wherein the at least one conductive layer increases the mechanical stability of the semiconductor workpiece to be sufficient to resist the at least one back end process without damage.