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    Semiconductor Device and Manufacturing Method Therefor
    11.
    发明申请
    Semiconductor Device and Manufacturing Method Therefor 有权
    半导体器件及其制造方法

    公开(公告)号：US20140353667A1

    公开(公告)日：2014-12-04

    申请号：US13906738

    申请日：2013-05-31

    Applicant: Infineon Technologies AG

    Inventor： Jens Konrath ,  Hans-Joachim Schulze ,  Roland Rupp ,  Wolfgang Werner ,  Frank Pfirsch

    IPC: H01L29/812 ,  H01L29/04 ,  H01L29/66 ,  H01L29/16

    CPC classification number: H01L29/66909 ,  H01L29/04 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/47 ,  H01L29/66068 ,  H01L29/66431 ,  H01L29/66734 ,  H01L29/66787 ,  H01L29/66848 ,  H01L29/7827 ,  H01L29/8122 ,  H01L29/872

    Abstract: A field-effect semiconductor device having a semiconductor body with a main surface is provided. The semiconductor body includes, in a vertical cross-section substantially orthogonal to the main surface, a drift layer of a first conductivity type, a semiconductor mesa of the first conductivity type adjoining the drift layer, substantially extending to the main surface and having two side walls, and two second semiconductor regions of a second conductivity type arranged next to the semiconductor mesa. Each of the two second semiconductor regions forms a pn-junction at least with the drift layer. A rectifying junction is formed at least at one of the two side walls of the mesa. Further, a method for producing a heterojunction semiconductor device is provided.

    Abstract translation: 提供了具有主表面的半导体本体的场效应半导体器件。 半导体本体在基本上垂直于主表面的垂直横截面中包括第一导电类型的漂移层，邻接漂移层的第一导电类型的半导体台面，基本上延伸到主表面并具有两个侧面 壁，以及布置在半导体台面旁边的第二导电类型的两个第二半导体区域。 两个第二半导体区域中的每一个至少与漂移层形成pn结。 在台面的两个侧壁中的至少一个侧面上形成整流结。 此外，提供了一种异质结半导体器件的制造方法。

    Method of Manufacturing a Reduced Free-Charge Carrier Lifetime Semiconductor Structure
    12.
    发明申请
    Method of Manufacturing a Reduced Free-Charge Carrier Lifetime Semiconductor Structure 有权
    制造减少自由载流子寿命半导体结构的方法

    公开(公告)号：US20140213022A1

    公开(公告)日：2014-07-31

    申请号：US14228330

    申请日：2014-03-28

    Applicant: Infineon Technologies AG

    Inventor： Holger Ruething ,  Hans-Joachim Schulze ,  Frank Hille ,  Frank Pfirsch

    IPC: H01L29/66

    CPC classification number: H01L29/66348 ,  H01L27/0611 ,  H01L29/167 ,  H01L29/32 ,  H01L29/7397

    Abstract: A method of manufacturing a reduced free-charge carrier lifetime semiconductor structure includes forming a plurality of transistor gate structures in trenches arranged in a semiconductor substrate, forming a body region between adjacent ones of the transistor gate structures and forming an end-of-range irradiation region between adjacent ones of the transistor gate structures, the end-of-range irradiation region having a plurality of vacancies.

    Abstract translation: 一种制造减小的自由电荷载流子寿命半导体结构的方法包括在布置在半导体衬底中的沟槽中形成多个晶体管栅极结构，在相邻的晶体管栅极结构之间形成体区，并形成距离范围 所述晶体管栅极结构中的相邻晶体管栅极结构之间的区域，所述端部范围照射区域具有多个空位。

    SEMICONDUCTOR DEVICE HAVING A TRENCH GATE AND METHOD FOR MANUFACTURING
    14.
    发明申请
    SEMICONDUCTOR DEVICE HAVING A TRENCH GATE AND METHOD FOR MANUFACTURING 审中-公开
    具有TRENCH门的半导体器件和制造方法

    公开(公告)号：US20130193510A1

    公开(公告)日：2013-08-01

    申请号：US13802861

    申请日：2013-03-14

    Applicant: Infineon Technologies AG

    Inventor： Christian Foerster ,  Georg Ehrentraut ,  Frank Pfirsch ,  Thomas Raker

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/4236 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/7827

    Abstract: A semiconductor device having a trench gate and method for manufacturing is disclosed. One embodiment includes a first semiconductor area and a second semiconductor area, a semiconductor body area between the first semiconductor area and the second semiconductor area, and a gate arranged in a trench and separated from the semiconductor body by an insulation layer, wherein the trench has a top trench portion which extends from the semiconductor surface at least to a depth which is greater than a depth of the first semiconductor area, wherein the trench further has a bottom trench portion extending subsequent to the top trench portion at least up to the second semiconductor area, and wherein the top trench portion has a first lateral dimension and the bottom trench portion has a second lateral dimension which is greater than the first lateral dimension.

    Abstract translation: 公开了一种具有沟槽栅的半导体器件及其制造方法。 一个实施例包括第一半导体区域和第二半导体区域，第一半导体区域和第二半导体区域之间的半导体主体区域以及布置在沟槽中并且通过绝缘层与半导体本体分离的栅极，其中沟槽具有 至少从所述半导体表面延伸到比所述第一半导体区域的深度大的深度的顶部沟槽部分，其中所述沟槽还具有在所述顶部沟槽部分之后延伸的底部沟槽部分，所述顶部沟槽部分至少直到所述第二半导体 并且其中顶部沟槽部分具有第一横向尺寸，并且底部沟槽部分具有大于第一横向尺寸的第二横向尺寸。

    METHOD OF PRODUCING A HIGH-VOLTAGE-RESISTANT SEMICONDUCTOR COMPONENT HAVING VERTICALLY CONDUCTIVE SEMICONDUCTOR BODY AREAS AND A TRENCH STRUCTURE
    17.
    发明申请
    METHOD OF PRODUCING A HIGH-VOLTAGE-RESISTANT SEMICONDUCTOR COMPONENT HAVING VERTICALLY CONDUCTIVE SEMICONDUCTOR BODY AREAS AND A TRENCH STRUCTURE 审中-公开
    制造具有垂直导电半导体体区域的高电压半导体元件的方法和一种TRENCH结构

    公开(公告)号：US20140203349A1

    公开(公告)日：2014-07-24

    申请号：US14138167

    申请日：2013-12-23

    Applicant: Infineon Technologies AG

    Inventor： Frank Pfirsch

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/7815 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/41 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/7802

    Abstract: A high-voltage-resistant semiconductor component (1) has vertically conductive semiconductor areas (17) and a trench structure (5). These vertically conductive semiconductor areas are formed from semiconductor body areas (10) of a first conductivity type and are surrounded by a trench structure (5) on the upper face (6) of the semiconductor component. For this purpose the trench structure has a base (7) and a wall area (8) and is filled with a material (9) with a relatively high dielectric constant (εr). The base area (7) of the trench structure (5) is provided with a heavily doped semiconductor material (11) of the same conductivity type as the lightly doped semiconductor body areas (17), and/or having a metallically conductive material

    Abstract translation: 耐高压半导体元件（1）具有垂直导电半导体区域（17）和沟槽结构（5）。 这些垂直导电半导体区域由第一导电类型的半导体主体区域（10）形成，并被半导体部件的上表面（6）上的沟槽结构（5）围绕。 为此目的，沟槽结构具有基部（7）和壁区域（8），并且填充有具有较高介电常数的材料（9）。 沟槽结构（5）的基区（7）设置有与轻掺杂半导体体区（17）相同导电类型的重掺杂半导体材料（11）和/或具有金属导电材料

    RC IGBT and Method of Operating an RC IGBT
    18.
    发明申请
    RC IGBT and Method of Operating an RC IGBT 有权

    公开(公告)号：US20250006729A1

    公开(公告)日：2025-01-02

    申请号：US18754430

    申请日：2024-06-26

    Applicant: Infineon Technologies AG

    Inventor： Roman Baburske ,  Frank Pfirsch

    IPC: H01L27/07 ,  H01L29/739 ,  H01L29/861

    Abstract: An RC IGBT includes, in a single chip, an active region configured to conduct both a forward load current and a reverse load current between a first load terminal at a front side of a semiconductor body of the RC IGBT and a second load terminal at a back side of the semiconductor body. The active region is separated into at least: an IGBT-only region, at least 90% of which is configured to conduct, based on a first control signal, only the forward load current; an RC IGBT region, at least 90% of which is configured to conduct the reverse load current and, based on a second control signal, the forward load current; and a hybrid region, at least 90% of which is configured to conduct, based on both the first control signal and the second control signal, the forward load current.

    METHOD OF OPERATING A POWER TRANSISTOR FORMED BY A PLURALITY OF TRANSISTOR CELLS ELECTRICALLY CONNECTED IN PARALLEL
    19.
    发明申请
    METHOD OF OPERATING A POWER TRANSISTOR FORMED BY A PLURALITY OF TRANSISTOR CELLS ELECTRICALLY CONNECTED IN PARALLEL 有权

    公开(公告)号：US20240405094A1

    公开(公告)日：2024-12-05

    申请号：US18800308

    申请日：2024-08-12

    Applicant: Infineon Technologies AG

    Inventor： Frank Pfirsch

    IPC: H01L29/51 ,  H01L29/40 ,  H01L29/739 ,  H01L29/78

    Abstract: A power transistor is formed by a plurality of transistor cells electrically connected in parallel. Each transistor cell includes a gate structure including a gate electrode coupled to a control terminal and a gate dielectric stack, the gate dielectric stack including a ferroelectric insulator. A method of operating the power transistor includes: switching the power transistor in a normal operating mode by applying a switching control signal to the control terminal, the switching control signal having a maximum voltage and a minimum voltage; and setting the ferroelectric insulator into a defined polarization state by applying a first voltage pulse to the control terminal, the first voltage pulse exceeding the maximum voltage of the switching control signal.

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