公开(公告)号：US09633927B2

公开(公告)日：2017-04-25

申请号：US13966375

申请日：2013-08-14

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Alfred Haimerl ,  Angela Kessler ,  Michael Bauer

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L23/48 ,  H01L23/49531 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/13033 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip arrangement includes semiconductor chips coupled to opposing sides of an insulating layer. The arrangement includes a first semiconductor chip having a first chip surface presenting a first chip conductive region. An electrically insulating layer includes a first layer surface presenting a first layer conductive region, and a second, opposing surface presenting a second layer conductive region. The electrically insulating layer is coupled to the first semiconductor chip by applying the first layer conductive region to the first chip conductive region. The electrically insulating layer is then coupled to the second chip conductive region by applying the second layer conductive region to the second chip conductive region.

公开(公告)号：US09576935B2

公开(公告)日：2017-02-21

申请号：US14254214

申请日：2014-04-16

Applicant: Infineon Technologies AG

Inventor： Michael Bauer ,  Ludwig Heitzer ,  Christian Stuempfl

IPC: H01L23/48 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49541 ,  H01L23/49548 ,  H01L25/0655 ,  H01L25/50 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating semiconductor packages includes providing a first substrate having an aperture, providing a first semiconductor chip, connecting the first semiconductor chip to the first substrate, filling the aperture with a first insulating material and encapsulating the semiconductor chip with a second insulating material to create a first encapsulation body.

Abstract translation: 一种制造半导体封装的方法包括提供具有孔径的第一衬底，提供第一半导体芯片，将第一半导体芯片连接到第一衬底，用第一绝缘材料填充孔，并用半导体芯片封装第二绝缘材料 创建第一个封装体。

公开(公告)号：US20160126227A1

公开(公告)日：2016-05-05

申请号：US14926892

申请日：2015-10-29

Applicant: Infineon Technologies AG

Inventor： Michael Bauer ,  Ludwig Heitzer ,  Christian Stuempfl

IPC: H01L25/16 ,  H01L21/78 ,  H01L21/02 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/16 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02266 ,  H01L21/78 ,  H01L23/485 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/20 ,  H01L24/24 ,  H01L24/27 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L25/04 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/273 ,  H01L2224/274 ,  H01L2224/291 ,  H01L2224/3201 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83801 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1461 ,  H01L2924/206 ,  H01L2924/2064 ,  H01L2224/27 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A method for fabricating an electronic device includes providing a first semiconductor chip and a second semiconductor chip. The first semiconductor chip has a first semiconductor die and a first solder interconnect layer applied to a main face of the first semiconductor die. The second semiconductor chip has a second semiconductor die, an insulating layer applied to a main face of the second semiconductor die, and a second solder interconnect layer applied to the insulating layer. The method further includes attaching the first semiconductor chip with the first solder interconnect layer to a first carrier and attaching the second semiconductor chip with the second solder interconnect layer to a second carrier.

Abstract translation: 一种制造电子器件的方法包括提供第一半导体芯片和第二半导体芯片。 第一半导体芯片具有施加到第一半导体管芯的主面的第一半导体管芯和第一焊料互连层。 第二半导体芯片具有第二半导体管芯，施加到第二半导体管芯的主面的绝缘层和施加到绝缘层的第二焊料互连层。 该方法还包括将具有第一焊料互连层的第一半导体芯片附接到第一载体并且将第二半导体芯片与第二焊料互连层附接到第二载体。

公开(公告)号：US20190385866A1

公开(公告)日：2019-12-19

申请号：US16007038

申请日：2018-06-13

Applicant: Infineon Technologies AG

Inventor： Rabie Djemour ,  Michael Bauer ,  Stefan Miethaner

IPC: H01L21/56 ,  H01L21/67 ,  H01L23/29

Abstract: A method for manipulating ions contained in an encapsulation material for a semiconductor device is provided. The method includes processing the encapsulation material and applying an electric field to the encapsulation material before the encapsulation material is finally cured. The ions contained in the encapsulation material have a mobility that decreases as the encapsulation material cures. By applying the electric field to the encapsulation material before the encapsulation material is finally cured, the amount of ions contained in the encapsulation material is reduced and/or the ions contained are concentrated in one or more regions of the encapsulation material. Corresponding apparatuses and semiconductor packages manufactured by the method are also described.

公开(公告)号：US10461056B2

公开(公告)日：2019-10-29

申请号：US15600857

申请日：2017-05-22

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Michael Bauer ,  Jochen Dangelmaier ,  Reimund Engl ,  Johann Gatterbauer ,  Frank Hille ,  Michael Huettinger ,  Werner Kanert ,  Heinrich Koerner ,  Brigitte Ruehle ,  Francisco Javier Santos Rodriguez ,  Antonio Vellei

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/29 ,  H01L21/02 ,  H01L23/495

Abstract: In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.

公开(公告)号：US20210082861A1

公开(公告)日：2021-03-18

申请号：US17090941

申请日：2020-11-06

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Michael Bauer ,  Jochen Dangelmaier ,  Reimund Engl ,  Johann Gatterbauer ,  Frank Hille ,  Michael Huettinger ,  Werner Kanert ,  Heinrich Koerner ,  Brigitte Ruehle ,  Francisco Javier Santos Rodriguez ,  Antonio Vellei

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/29 ,  H01L21/02 ,  H01L23/495

Abstract: In various embodiments, a method of forming an electrical contact is provided. The method may include depositing, by atomic layer deposition, a passivation layer over at least a region of a metal surface, wherein the passivation layer may include aluminum oxide, and electrically contacting the region of the metal surface with a metal contact structure, wherein the metal contact structure may include copper.

公开(公告)号：US20190287875A1

公开(公告)日：2019-09-19

申请号：US16431808

申请日：2019-06-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Heinrich Koerner ,  Michael Bauer ,  Reimund ENGL ,  Michael Huettinger ,  Werner Kanert ,  Joachim Mahler ,  Brigitte Ruehle

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/495

Abstract: In various embodiments, methods for forming a chip package are provided. The chip package may include a chip comprising a chip metal surface, a metal contact structure electrically contacting the chip metal surface, a packaging material at least partially encapsulating the chip and the metal contact structure, and a chemical compound physically contacting the packaging material and at least one of the chip metal surface and the metal contact structure, wherein the chemical compound may be configured to improve an adhesion between the metal contact structure and the packaging material and/or between the chip metal surface and the packaging material, as compared with an adhesion in an arrangement without the chemical compound, wherein the chemical compound is essentially free from functional groups comprising sulfur, selenium or tellurium.

公开(公告)号：US20170338164A1

公开(公告)日：2017-11-23

申请号：US15599492

申请日：2017-05-19

Applicant: Infineon Technologies AG

Inventor： Heinrich Koerner ,  Michael Bauer ,  Reimund Engl ,  Michael Huettinger ,  Werner Kanert ,  Joachim Mahler ,  Brigitte Ruehle

IPC: H01L23/29 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/293 ,  H01L21/56 ,  H01L23/295 ,  H01L23/296 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48647 ,  H01L2224/73265 ,  H01L2924/01029 ,  H01L2924/181 ,  H01L2924/365 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2224/45664 ,  H01L2224/45644 ,  H01L2224/45669

Abstract: In various embodiments, a chip package is provided. The chip package may include a chip including a chip metal surface, a metal contact structure electrically contacting the chip metal surface, and packaging material including a contact layer being in physical contact with the chip metal surface and/or with the metal contact structure; wherein at least in the contact layer of the packaging material, a summed concentration of chemically reactive sulfur, chemically reactive selenium and chemically reactive tellurium is less than 10 atomic parts per million.

公开(公告)号：US20150097282A1

公开(公告)日：2015-04-09

申请号：US14569958

申请日：2014-12-15

Applicant: Infineon Technologies AG

Inventor： Michael Bauer ,  Alfred Haimerl ,  Angela Kessler ,  Wolfgang Schober

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/49838 ,  H01L21/56 ,  H01L23/12 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3157 ,  H01L23/3171 ,  H01L23/492 ,  H01L23/49562 ,  H01L23/49805 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: A chip package is provided, the chip package including: a chip carrier; a chip disposed over and electrically connected to a chip carrier top side; an electrically insulating material disposed over and at least partially surrounding the chip; one or more electrically conductive contact regions formed over the electrically insulating material and in electrical connection with the chip; a further electrically insulating material disposed over a chip carrier bottom side; wherein an electrically conductive contact region on the chip carrier bottom side is released from the further electrically insulating material.

Abstract translation: 提供芯片封装，芯片封装包括：芯片载体; 芯片布置在芯片载体顶侧并电连接到芯片载体顶侧; 设置在芯片上并且至少部分地围绕芯片的电绝缘材料; 形成在所述电绝缘材料上并与所述芯片电连接的一个或多个导电接触区域; 设置在芯片载体底侧上的另外的电绝缘材料; 其中芯片载体底侧上的导电接触区域从另外的电绝缘材料释放。

公开(公告)号：US20130105992A1

公开(公告)日：2013-05-02

申请号：US13721957

申请日：2012-12-20

Applicant: Infineon Technologies AG

Inventor： Michael Bauer ,  Thomas Engling ,  Alfred Halmerl ,  Angela Kessler ,  Joachim Mahler ,  Wolfgang Schober

IPC: H01L23/538

CPC classification number: H01L23/538 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L25/0657 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/24146 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

Abstract: A semiconductor component including a stack of semiconductor chips, the semiconductor chips being fixed cohesively one on top of another, is disclosed. The contact areas of the semiconductor chips are led as far as the edges of the semiconductor chips and conductor portions extend at least from an upper edge to a lower edge of the edge sides of the semiconductor chips in order to electrically connect the contact area of the stacked semiconductor chips to one another.

Abstract translation: 公开了一种包括半导体芯片的堆叠的半导体部件，半导体芯片一体地固定在另一个之上。 半导体芯片的接触区域被引导直到半导体芯片和导体部分的边缘至少从半导体芯片的边缘侧的上边缘延伸到下边缘，以便电连接半导体芯片的接触区域 堆叠的半导体芯片彼此。