公开(公告)号：US20150022924A1

公开(公告)日：2015-01-22

申请号：US13944288

申请日：2013-07-17

Applicant: Infineon Technologies AG

Inventor： Jens Barrenscheen ,  Roderick McConnell ,  Peter Ossimitz

IPC: G01R31/40 ,  H02H7/22

CPC classification number: G01R31/40 ,  G01R19/16552 ,  G06F1/28 ,  H02H7/22

Abstract: The disclosure relates to a circuitry including a first contact connected to a power supply, a first compare unit connected to the first contact and to a first reference signal, wherein the first compare unit is configured to compare a voltage at the first contact with the first reference signal and provide a first output signal for further processing.

Abstract translation: 本公开涉及包括连接到电源的第一触点，连接到第一触点的第一比较单元和第一参考信号的电路，其中第一比较单元被配置为将第一触点处的电压与第一触点 并提供用于进一步处理的第一输出信号。

公开(公告)号：US20140264814A1

公开(公告)日：2014-09-18

申请号：US14288726

申请日：2014-05-28

Applicant: Infineon Technologies AG

Inventor： Peter Ossimitz ,  Matthias Van Daak ,  Dirk Hesidenz

IPC: H01L23/00

CPC classification number: H01L24/09 ,  G11C5/06 ,  H01L22/32 ,  H01L23/50 ,  H01L23/5286 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/02379 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/06135 ,  H01L2224/06137 ,  H01L2224/09179 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: Embodiments of the present invention relate to a semiconductor chip comprising a plurality of contact pads, which are arranged in an edge area on a surface of the semiconductor chip. In a semiconductor area of the semiconductor chip, every contact pad of the plurality of contact pads has an associated pad cell provided, which includes at least one of a driver or a receiver and is configured to drive output signals or receive input signals on its associated contact pad, if the driver or receiver is connected to the contact pad. Additionally, for a contact pad which is used as a supply contact pad, the driver or receiver of the associated pad cell is not connected to the contact pad or any other contact pad for driving output signals or receiving input signals on the same.

Abstract translation: 本发明的实施例涉及一种包括多个接触焊盘的半导体芯片，其布置在半导体芯片的表面上的边缘区域中。 在半导体芯片的半导体区域中，多个接触焊盘的每个接触焊盘具有提供的相关联的焊盘单元，其包括驱动器或接收器中的至少一个，并且被配置为驱动输出信号或接收其相关联的输入信号 接触垫，如果驱动器或接收器连接到接触垫。 此外，对于用作供电接触焊盘的接触焊盘，相关联的焊盘单元的驱动器或接收器不连接到接触焊盘或用于驱动输出信号或接收其上的输入信号的接触焊盘或任何其它接触焊盘。

公开(公告)号：US09859251B2

公开(公告)日：2018-01-02

申请号：US15012086

申请日：2016-02-01

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Peter Ossimitz

IPC: H01L23/495 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/19104

Abstract: A semiconductor device package includes an electronic component and an electrical interconnect. The electronic component is attached to the electrical interconnect. The electrical interconnect is configured to electrically couple the electronic component to external terminals of the semiconductor device package. The electrical interconnect has a first main face facing the electronic component and a second main face opposite the first main face. The semiconductor device package further includes a first semiconductor chip facing the second main face of the electrical interconnect.

公开(公告)号：US09385059B2

公开(公告)日：2016-07-05

申请号：US14011772

申请日：2013-08-28

Applicant: Infineon Technologies AG

Inventor： Peter Ossimitz ,  Juergen Schaefer ,  Liu Chen ,  Markus Dinkel ,  Stefan Macheiner

IPC: H05K7/20 ,  H01L23/34 ,  H01L21/48 ,  H05K3/32 ,  H01L23/367 ,  H01L23/40 ,  H05K3/28 ,  H05K5/00 ,  H01L23/31 ,  H01L23/427 ,  H01L23/498 ,  H05K1/02

CPC classification number: H01L23/34 ,  H01L21/4882 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/4006 ,  H01L23/4093 ,  H01L23/427 ,  H01L23/49822 ,  H01L2023/405 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/13055 ,  H05K1/0206 ,  H05K1/0209 ,  H05K3/284 ,  H05K3/32 ,  H05K5/0034 ,  H05K7/20854 ,  H05K2201/10166 ,  Y10T29/49146 ,  H01L2924/00

Abstract: An electronic device comprises a substrate, at least one electronic chip mounted on and electrically connected to the substrate and being configured as a system control unit for controlling a connected system, a heat removal structure thermally connected to the at least one electronic chip and configured for removing heat generated by the at least one electronic chip upon operation of the electronic device, and an overmolding structure configured for at least partially encapsulating at least the at least one electronic chip and the substrate.

公开(公告)号：US09362187B2

公开(公告)日：2016-06-07

申请号：US13745537

申请日：2013-01-18

Applicant: Infineon Technologies AG

Inventor： Peter Ossimitz

IPC: H01L23/58 ,  H01L23/48 ,  G01R31/26 ,  H01L21/66 ,  H01L23/498

CPC classification number: H01L22/32 ,  H01L23/49838 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: A chip package includes an integrated circuit chip. A first group of terminal pads of the chip package is electrically connected to the integrated circuit chip and a second group of terminal pads of the chip package is electrically connected to the integrated circuit chip. The first and second groups of terminal pads are arranged on a common terminal surface of the chip package. A pad size of a terminal pad of the first group of terminal pads is greater than a pad size of a terminal pad of the second group of terminal pads.

Abstract translation: 芯片封装包括集成电路芯片。 芯片封装的第一组端子焊盘电连接到集成电路芯片，并且芯片封装的第二组端子焊盘电连接到集成电路芯片。 第一和第二组端子焊盘被布置在芯片封装的公共端子表面上。 第一组端子焊盘的端子焊盘的焊盘尺寸大于第二组端子焊盘的端子焊盘的焊盘尺寸。

公开(公告)号：US20150062825A1

公开(公告)日：2015-03-05

申请号：US14011772

申请日：2013-08-28

Applicant: Infineon Technologies AG

Inventor： Peter Ossimitz ,  Juergen Schaefer ,  Liu Chen ,  Markus Dinkel ,  Stefan MacHeiner

IPC: H01L23/34 ,  H05K3/32 ,  H01L21/48

CPC classification number: H01L23/34 ,  H01L21/4882 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/4006 ,  H01L23/4093 ,  H01L23/427 ,  H01L23/49822 ,  H01L2023/405 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/13055 ,  H05K1/0206 ,  H05K1/0209 ,  H05K3/284 ,  H05K3/32 ,  H05K5/0034 ,  H05K7/20854 ,  H05K2201/10166 ,  Y10T29/49146 ,  H01L2924/00

Abstract: An electronic device comprises a substrate, at least one electronic chip mounted on and electrically connected to the substrate and being configured as a system control unit for controlling a connected system, a heat removal structure thermally connected to the at least one electronic chip and configured for removing heat generated by the at least one electronic chip upon operation of the electronic device, and an overmolding structure configured for at least partially encapsulating at least the at least one electronic chip and the substrate.

Abstract translation: 电子设备包括基板，安装在基板上并与其电连接的至少一个电子芯片，并且被配置为用于控制连接的系统的系统控制单元，热连接到所述至少一个电子芯片的散热结构， 在电子设备操作时去除由至少一个电子芯片产生的热量，以及被配置用于至少部分地封装至少一个电子芯片和基板的二次模制结构。

公开(公告)号：US20140332953A1

公开(公告)日：2014-11-13

申请号：US13892367

申请日：2013-05-13

Applicant: Infineon Technologies AG

Inventor： Peter Ossimitz ,  Robert Bauer ,  Tobias Jacobs

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49811 ,  H01L21/76885 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/1134 ,  H01L2224/11903 ,  H01L2224/13005 ,  H01L2224/13017 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1411 ,  H01L2224/17107 ,  H01L2224/81193 ,  H01L2924/0002 ,  H01L2924/381 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/207 ,  H01L2924/01047

Abstract: A chip arrangement may include: a chip including a plurality of electrical nets, wherein each electrical net includes at least one bonding pad; and a plurality of pillars formed on the at least one bonding pad of a majority of the plurality of electrical nets, wherein the plurality of pillars may be configured to connect the at least one bonding pad of the majority of the plurality of electrical nets to a chip-external connection region.

Abstract translation: 芯片布置可以包括：包括多个电网的芯片，其中每个电网包括至少一个焊盘; 以及形成在所述多个电网中的大多数的所述至少一个焊盘上的多个柱，其中所述多个柱可以被配置为将所述多个电网中的大多数的所述至少一个焊盘连接到 芯片外部连接区域。

公开(公告)号：US20140206109A1

公开(公告)日：2014-07-24

申请号：US13745550

申请日：2013-01-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Peter Ossimitz ,  Matthias von Daak ,  Gottfried Beer

IPC: H01L21/66

CPC classification number: H01L22/10 ,  G01R31/2884 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: A method of producing and testing a chip package is described. The chip package to be produced includes a semiconductor chip containing an integrated circuit and a reinforcing structure attached to the semiconductor chip. Further, the chip package has a lower main face and an upper main face opposite to the lower main face, wherein the lower main face is at least partly formed by an exposed surface of the semiconductor chip and the upper main face is formed by a terminal surface of the reinforcing structure on which external terminal pads of the chip package are arranged. After production, the package is subjected to a package-level burn-in test.

Abstract translation: 描述了制造和测试芯片封装的方法。 要制造的芯片封装包括一个包含集成电路的半导体芯片和一个附着在半导体芯片上的加强结构。 此外，芯片封装具有与下主面相对的下主面和上主面，其中下主面至少部分地由半导体芯片的暴露表面形成，并且上主面由终端形成 所述加强结构的表面布置有所述芯片封装的外部端子焊盘。 生产后，对包装进行封装级老化测试。