公开(公告)号：US11842938B2

公开(公告)日：2023-12-12

申请号：US17538162

申请日：2021-11-30

Applicant: Infineon Technologies AG

Inventor： Jens Peter Konrath ,  Wolfgang Bergner ,  Romain Esteve ,  Richard Gaisberger ,  Florian Grasse ,  Jochen Hilsenbeck ,  Ravi Keshav Joshi ,  Stefan Kramp ,  Stefan Krivec ,  Grzegorz Lupina ,  Hiroshi Narahashi ,  Andreas Voerckel ,  Stefan Woehlert

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L29/16 ,  H01L29/861 ,  H01L29/78 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/3192 ,  H01L21/56 ,  H01L21/76841 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/53223 ,  H01L29/1608 ,  H01L29/7811 ,  H01L29/8611

Abstract: A semiconductor device includes a contact metallization layer that includes aluminum and is arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, an organic passivation layer comprising a first part that is arranged on the contact metallization layer, and a second part that is arranged on the inorganic passivation structure, a first layer structure including a first part that is in contact with the contact metallization layer, a second part that is contact with the inorganic passivation structure, and a third part that is disposed on the semiconductor substrate laterally between the inorganic passivation structure and the organic passivation layer.

公开(公告)号：US20220093483A1

公开(公告)日：2022-03-24

申请号：US17538162

申请日：2021-11-30

Applicant: Infineon Technologies AG

Inventor： Jens Peter Konrath ,  Wolfgang Bergner ,  Romain Esteve ,  Richard Gaisberger ,  Florian Grasse ,  Jochen Hilsenbeck ,  Ravi Keshav Joshi ,  Stefan Kramp ,  Stefan Krivec ,  Grzegorz Lupina ,  Hiroshi Narahashi ,  Andreas Voerckel ,  Stefan Woehlert

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L29/16 ,  H01L29/861 ,  H01L29/78 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor device includes a contact metallization layer that includes aluminum and is arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, an organic passivation layer comprising a first part that is arranged on the contact metallization layer, and a second part that is arranged on the inorganic passivation structure, a first layer structure including a first part that is in contact with the contact metallization layer, a second part that is contact with the inorganic passivation structure, and a third part that is disposed on the semiconductor substrate laterally between the inorganic passivation structure and the organic passivation layer.

公开(公告)号：US11043383B2

公开(公告)日：2021-06-22

申请号：US16422373

申请日：2019-05-24

Applicant: Infineon Technologies AG

Inventor： Stefan Krivec ,  Ronny Kern ,  Stefan Kramp ,  Gregor Langer ,  Hannes Winkler ,  Stefan Woehlert

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/45 ,  H01L21/02

Abstract: A process for producing an electrical contact with a first metal layer and at least one second metal layer on a silicon carbide substrate includes removing at least some of the carbon residue by a chemical cleaning process, to clean the first metal layer. The first metal layer and/or the at least one second metal layer may be generated by sputtering deposition.

公开(公告)号：US09929111B2

公开(公告)日：2018-03-27

申请号：US15461500

申请日：2017-03-17

Applicant: Infineon Technologies AG

Inventor： Martin Mischitz ,  Markus Heinrici ,  Barbara Eichinger ,  Manfred Schneegans ,  Stefan Krivec

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/02 ,  H01L23/532 ,  H01L21/762

CPC classification number: H01L24/03 ,  H01L21/02203 ,  H01L21/02513 ,  H01L21/76259 ,  H01L23/53238 ,  H01L24/05 ,  H01L2224/0331 ,  H01L2224/0345 ,  H01L2224/03505 ,  H01L2224/03602 ,  H01L2224/03616 ,  H01L2224/0384 ,  H01L2224/05541 ,  H01L2224/05551 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2924/3511 ,  H01L2924/35121

Abstract: A method of manufacturing a layer structure includes: forming a first layer over a substrate; planarizing the first layer to form a planarized surface of the first layer; and forming a second layer over the planarized surface; wherein a porosity of the first layer is greater than a porosity of the substrate and greater than a porosity of the second layer; wherein the second layer is formed by physical vapor deposition; and wherein the first layer and the second layer are formed from the same solid material.

公开(公告)号：US20170243828A1

公开(公告)日：2017-08-24

申请号：US15427428

申请日：2017-02-08

Applicant: Infineon Technologies AG

Inventor： Jochen Hilsenbeck ,  Jens Peter Konrath ,  Stefan Krivec

IPC: H01L23/532 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/28575 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76852 ,  H01L23/532 ,  H01L23/564 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/8083 ,  H01L2224/0345 ,  H01L2224/0347 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/0391 ,  H01L2224/03914 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05188 ,  H01L2224/05551 ,  H01L2224/05561 ,  H01L2224/05566 ,  H01L2224/05599 ,  H01L2224/05688 ,  H01L2224/45099 ,  H01L2224/85375 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/12036 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/0496 ,  H01L2924/01042 ,  H01L2924/01029 ,  H01L2924/01014 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a semiconductor body with a front face and a back face, having an active zone located at the front face, a front surface metallization layer having a front face and a back face directed towards the active zone, the front surface metallization layer being provided on the front face of the semiconductor body and being electrically connected to the active zone, and a first barrier layer, including amorphous molybdenum nitride, located between the active zone and the metallization layer. Further, a method for producing such a device is provided.

公开(公告)号：US20160126197A1

公开(公告)日：2016-05-05

申请号：US14932548

申请日：2015-11-04

Applicant: Infineon Technologies AG

Inventor： Kurt Matoy ,  Dirk Ahlers ,  Ulrike Fastner ,  Petra Fischer ,  Karl-Heinz Gasser ,  Stephan Henneck ,  Stefan Krivec ,  Florian Weilnboeck

IPC: H01L23/00 ,  H01L23/495 ,  H01L29/45 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/32 ,  H01L24/83 ,  H01L29/45 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/8321 ,  H01L2224/83815 ,  H01L2924/014 ,  H01L2924/3511 ,  H01L2924/37001

Abstract: A semiconductor device includes a semiconductor chip having a first main surface and a second main surface. A chip electrode is disposed on the first main surface. The chip electrode includes a first metal layer and wherein the first metal layer is arranged between the semiconductor chip and the second metal layer.

Abstract translation: 半导体器件包括具有第一主表面和第二主表面的半导体芯片。 芯片电极设置在第一主表面上。 芯片电极包括第一金属层，并且其中第一金属层布置在半导体芯片和第二金属层之间。

公开(公告)号：US11195713B2

公开(公告)日：2021-12-07

申请号：US16426051

申请日：2019-05-30

Applicant: Infineon Technologies AG

Inventor： Joachim Hirschler ,  Georg Ehrentraut ,  Christoffer Erbert ,  Klaus Goeschl ,  Markus Heinrici ,  Michael Hutzler ,  Wolfgang Koell ,  Stefan Krivec ,  Ingmar Neumann ,  Mathias Plappert ,  Michael Roesner ,  Olaf Storbeck

IPC: H01L21/02 ,  H01L29/51 ,  H01L21/28 ,  H01L21/18 ,  H01L29/49

Abstract: In one aspect, a method of forming a silicon-insulator layer is provided. The method includes arranging a silicon structure in a plasma etch process chamber and applying a plasma to the silicon structure in the plasma etch process chamber at a temperature of the silicon structure equal to or below 100° C. The plasma includes a component and a halogen derivate, thereby forming the silicon-insulator layer. The silicon-insulator layer includes silicon and the component. In another aspect, a semiconductor device is provided having a silicon-insulator layer formed by the method.

公开(公告)号：US20210265168A1

公开(公告)日：2021-08-26

申请号：US17315943

申请日：2021-05-10

Applicant: Infineon Technologies AG

Inventor： Stefan Krivec ,  Ronny Kern ,  Stefan Kramp ,  Gregor Langer ,  Hannes Winkler ,  Stefan Woehlert

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/45 ,  H01L21/02

Abstract: A process for producing an electrical contact with a first metal layer and at least one second metal layer on a silicon carbide substrate includes removing at least some of the carbon residue by a cleaning process, to clean the first metal layer. The first metal layer and/or the at least one second metal layer may be generated by sputtering deposition.

公开(公告)号：US10393697B2

公开(公告)日：2019-08-27

申请号：US14930295

申请日：2015-11-02

Applicant: Infineon Technologies AG

Inventor： Sabine Gruber ,  Thomas Aichinger ,  Stefan Krivec ,  Thomas Ostermann

IPC: G01N27/447 ,  G01N27/453 ,  G01N27/27 ,  G01N27/414

Abstract: An apparatus for analyzing ion kinetics in a dielectric probe structure includes an ion reservoir abutting the dielectric probe structure and configured to supply mobile ions to the dielectric probe structure, a capacitor structure configured to generate an electric field in the dielectric probe structure along a vertical direction, and an electrode structure configured to generate an electrophoretic force on mobile ions in the dielectric probe structure along a lateral direction. A method for analyzing ion kinetics in the dielectric probe structure of the apparatus is also provided.

公开(公告)号：US10361096B2

公开(公告)日：2019-07-23

申请号：US15677091

申请日：2017-08-15

Applicant: Infineon Technologies AG

Inventor： Mathias Plappert ,  Stefan Krivec ,  Andreas Riegler ,  Karin Schrettlinger

IPC: H01L21/3215 ,  H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L23/29 ,  H01L29/66 ,  H01L29/739 ,  H01L29/40 ,  H01L29/06 ,  H01L29/417 ,  H01L29/74

Abstract: In various embodiments, a method is provided. The method includes forming a metallization layer above at least one first region of a substrate. After forming the metallization layer at least one second region of the substrate is free of the metallization layer. The method further includes forming a barrier layer above the at least one first region of the substrate and above the at least one second region of the substrate. The barrier layer in the at least one first region of the substrate directly adjoins the metallization layer. The method further includes removing the barrier layer in the at least one first region of the substrate by drive-in of the barrier layer into the metallization layer.