公开(公告)号：US20190304876A1

公开(公告)日：2019-10-03

申请号：US16284239

申请日：2019-02-25

Applicant: Intel Corporation

Inventor： Loke Yip Foo ,  Choong Kooi Chee

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/18 ,  H01L23/31 ,  H01L23/538 ,  H01L23/367 ,  H01L21/56

Abstract: Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.

公开(公告)号：US20170265306A1

公开(公告)日：2017-09-14

申请号：US15607612

申请日：2017-05-29

Applicant: INTEL CORPORATION

Inventor： Howe Yin Loo ,  Choong Kooi Chee

IPC: H05K1/18 ,  H01L23/13 ,  H01L23/367 ,  H01L23/498 ,  H01L25/065 ,  H05K1/14 ,  H05K3/30 ,  H01L23/427 ,  H05K3/34

CPC classification number: H05K1/181 ,  H01L23/13 ,  H01L23/3677 ,  H01L23/427 ,  H01L23/49827 ,  H01L25/0652 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/0652 ,  H05K1/141 ,  H05K1/144 ,  H05K1/182 ,  H05K1/183 ,  H05K3/30 ,  H05K3/3415 ,  H05K2201/09036 ,  H05K2201/09063 ,  H05K2201/09072 ,  H05K2201/10378 ,  H05K2201/10416 ,  H05K2201/10734 ,  Y02P70/611 ,  Y10T29/4913

Abstract: The present description relates to the field of fabricating microelectronic structures. The microelectronic structure may include a microelectronic substrate have an opening, wherein the opening may be formed through the microelectronic substrate or may be a recess formed in the microelectronic substrate. A microelectronic package may be attached to the microelectronic substrate, wherein the microelectronic package may include an interposer having a first surface and an opposing second surface. A microelectronic device may be attached to the interposer first surface and the interposer may be attached to the microelectronic substrate by the interposer first surface such that the microelectronic device extends into the opening. At least one secondary microelectronic device may be attached to the interposer second surface.

公开(公告)号：US09159714B2

公开(公告)日：2015-10-13

申请号：US14040642

申请日：2013-09-28

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Choong Kooi Chee ,  Seok Ling Lim

IPC: H01L23/48 ,  H01L25/18 ,  H01L25/00 ,  H01L23/538 ,  H01L23/498 ,  H01L23/14

CPC classification number: H01L25/18 ,  H01L23/147 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/538 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/25 ,  H01L24/73 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/06183 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/2518 ,  H01L2224/73259 ,  H01L2224/9222 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/014

Abstract: An apparatus including a die including a device side and an opposite backside, first contacts on the backside and a through vias from the device side to the first contacts and second contacts on the backside of the die or on at least two opposing sidewalls of the die; a secondary die coupled to the first plurality of contacts; and a carrier including carrier contact points operable for mounting the carrier to a substrate. A method including forming a first portion of a carrier adjacent a device side of a die and including carrier contact points operable for mounting the carrier to a substrate; and forming a second portion including second carrier contact points connected to contacts on the backside of the die or on at least two opposing sidewalls of the die; and coupling a secondary die to the second carrier contact points.

Abstract translation: 一种包括模具的设备，包括器件侧和相对的后侧，在后侧上的第一接触和从器件侧到第一接触件的通孔和在管芯的背面上的第二接触件或在管芯的至少两个相对的侧壁上 ; 耦合到所述第一多个触点的次模; 以及载体，其包括可操作用于将载体安装到基底的载体接触点。 一种方法，包括在模具的装置侧附近形成载体的第一部分，并且包括可操作以将载体安装到基底的载体接触点; 以及形成第二部分，所述第二部分包括连接到所述管芯的背面上的接触点或所述管芯的至少两个相对的侧壁上的第二载体接触点; 以及将次级管芯耦合到第二载体接触点。

公开(公告)号：US12237245B2

公开(公告)日：2025-02-25

申请号：US18089207

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Loke Yip Foo ,  Choong Kooi Chee

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538 ,  H01L25/18

Abstract: Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.

公开(公告)号：US12112997B2

公开(公告)日：2024-10-08

申请号：US18216040

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Choong Kooi Chee ,  Jackson Chung Peng Kong ,  Wai Ling Lee ,  Tat Hin Tan

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/822 ,  H01L23/00 ,  H01L23/48 ,  H01L25/16 ,  H01L49/02

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L21/8221 ,  H01L24/09 ,  H01L24/17 ,  H01L25/16 ,  H01L28/40

Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.

公开(公告)号：US11562959B2

公开(公告)日：2023-01-24

申请号：US16912638

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Loke Yip Foo ,  Teong Guan Yew ,  Choong Kooi Chee

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A dual-sided embedded multi-die interconnect bridge provides power and source conduits from the bridge bottom at a silicon portion, in short paths to dice on a die side of an integrated-circuit package substrate. Signal traces are in a metallization on the silicon portion of the dual-sided EMIB. Power, ground and signal vias all emanate from the dual-sided embedded multi-die interconnect bridge, with power and ground entering the bridge from central regions of the silicon portion.

公开(公告)号：US20210320051A1

公开(公告)日：2021-10-14

申请号：US17155757

申请日：2021-01-22

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Choong Kooi Chee ,  Jackson Chung Peng Kong ,  Wai Ling Lee ,  Tat Hin Tan

IPC: H01L23/48 ,  H01L25/16 ,  H01L23/00 ,  H01L21/768 ,  H01L21/822

Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.

公开(公告)号：US20200043831A1

公开(公告)日：2020-02-06

申请号：US16402482

申请日：2019-05-03

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Choong Kooi Chee ,  Jackson Chung Peng Kong ,  Tat Hin Tan ,  Wai Ling Lee

IPC: H01L23/48 ,  H01L25/16 ,  H01L23/00 ,  H01L21/768 ,  H01L21/822

Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.