公开(公告)号：US20180096891A1

公开(公告)日：2018-04-05

申请号：US15827491

申请日：2017-11-30

Applicant: INTEL CORPORATION

Inventor： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC: H01L21/768 ,  H01L29/423 ,  H01L21/28 ,  H01L21/283 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L29/45 ,  H01L29/16 ,  H01L29/08 ,  H01L23/535 ,  H01L23/528 ,  H01L23/522 ,  H01L21/311 ,  H01L21/285

CPC classification number: H01L21/76897 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US09929273B2

公开(公告)日：2018-03-27

申请号：US15528763

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Matthew V. Metz ,  Chandra S. Mohapatra ,  Gilbert Dewey ,  Nadia M. Rahhal-Orabi ,  Tahir Ghani ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Glenn A. Glass

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L21/306

CPC classification number: H01L29/7853 ,  H01L21/02532 ,  H01L21/02694 ,  H01L21/30625 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: An embodiment includes a microelectronic device comprising: a substrate comprising a raised portion and a non-raised portion, wherein a dielectric material is disposed adjacent the raised portion, an epitaxial sub-fin structure disposed on the raised portion, wherein a bottom portion of the epitaxial sub-fin structure comprises an asymmetric profile, and an epitaxial fin device structure disposed on the sub-fin structure. Other embodiments are described herein.

公开(公告)号：US09892967B2

公开(公告)日：2018-02-13

申请号：US15299106

申请日：2016-10-20

Applicant: INTEL CORPORATION

Inventor： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC: H01L21/28 ,  H01L21/285 ,  H01L23/535 ,  H01L29/45 ,  H01L29/16 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L29/08 ,  H01L23/522 ,  H01L21/283 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L21/76897 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US20170047452A1

公开(公告)日：2017-02-16

申请号：US15335269

申请日：2016-10-26

Applicant: INTEL CORPORATION

Inventor： Seiyon Kim ,  Daniel A. Simon ,  Nadia M. Rahhal-Orabi ,  Chul-Hyun Lim ,  Kelin J. Kuhn

IPC: H01L29/786 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/78696 ,  B82Y10/00 ,  H01L21/02603 ,  H01L21/823807 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78684

Abstract: A nanowire transistor of the present description may be produced with internal spacers formed by using sacrificial spacers during the fabrication thereof. Once the nanowire transistor is formed, the sacrificial spacers, which are position between the transistor gate and the source and drains (respectively), may be removed. The sacrificial material between channel nanowires of the nanowire transistor may then be removed and a dielectric material may be deposited to fill the spaces between the channel nanowires. The dielectric material not between the channel nanowires may be removed to form the internal spacers. External spacers, which are position between the transistor gate and the source and drains (respectively), may then be formed adjacent the internal spacers and transistor channel nanowires.

Abstract translation: 本描述的纳米线晶体管可以在其制造期间使用牺牲间隔物形成的内部间隔物来制造。 一旦形成了纳米线晶体管，就可以去除位于晶体管栅极和源极之间的排列（分别）的牺牲间隔物。 然后可以去除纳米线晶体管的沟道纳米线之间的牺牲材料，并且可以沉积介电材料以填充沟道纳米线之间的空间。 可以除去不在通道纳米线之间的电介质材料以形成内部间隔物。 位于晶体管栅极和源极之间的位置（分别）的外部间隔物可以随后形成在内部间隔物和晶体管沟道纳米线附近。

公开(公告)号：US09508796B2

公开(公告)日：2016-11-29

申请号：US14916093

申请日：2013-10-03

Applicant: INTEL CORPORATION

Inventor： Seiyon Kim ,  Daniel A. Simon ,  Nadia M. Rahhal-Orabi ,  Chul-Hyun Lim ,  Kelin J. Kuhn

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/161 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L29/78696 ,  B82Y10/00 ,  H01L21/02603 ,  H01L21/823807 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78684

Abstract: A nanowire transistor of the present description may be produced with internal spacers formed by using sacrificial spacers during the fabrication thereof. Once the nanowire transistor is formed, the sacrificial spacers, which are position between the transistor gate and the source and drains (respectively), may be removed. The sacrificial material between channel nanowires of the nanowire transistor may then be removed and a dielectric material may be deposited to fill the spaces between the channel nanowires. The dielectric material not between the channel nanowires may be removed to form the internal spacers. External spacers, which are position between the transistor gate and the source and drains (respectively), may then be formed adjacent the internal spacers and transistor channel nanowires.

Abstract translation: 本描述的纳米线晶体管可以在其制造期间使用牺牲间隔物形成的内部间隔物来制造。 一旦形成了纳米线晶体管，就可以去除位于晶体管栅极和源极之间的排列（分别）的牺牲间隔物。 然后可以去除纳米线晶体管的沟道纳米线之间的牺牲材料，并且可以沉积介电材料以填充沟道纳米线之间的空间。 可以除去不在通道纳米线之间的电介质材料以形成内部间隔物。 位于晶体管栅极和源极之间的位置（分别）的外部间隔物可以随后形成在内部间隔物和晶体管沟道纳米线附近。

公开(公告)号：US10580865B2

公开(公告)日：2020-03-03

申请号：US15776996

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Matthew V. Metz ,  Gilbert Dewey ,  Chandra S. Mohapatra ,  Nadia M. Rahhal-Orabi ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/205 ,  H01L29/78

Abstract: Embodiments of the present disclosure describe a semiconductor multi-gate transistor having a semi-conductor fin extending from a substrate and including a sub-fin region and an active region. The sub-fin region may include a dielectric material region under the gate to provide improved isolation. The dielectric material region may be formed during a replacement gate process by replacing a portion of a sub-fin region under the gate with the dielectric material region, followed by fabrication of a replacement gate structure. The sub-fin region may be comprised of group III-V semiconductor materials in various combinations and concentrations. The active region may be comprised of a different group III-V semiconductor material. The dielectric material region may be comprised of amorphous silicon. Other embodiments may be described and/or claimed.

公开(公告)号：US20190051558A1

公开(公告)日：2019-02-14

申请号：US16162186

申请日：2018-10-16

Applicant: Intel Corporation

Inventor： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L29/45 ,  H01L29/16 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L21/311 ,  H01L29/08 ,  H01L29/49 ,  H01L23/535 ,  H01L21/285 ,  H01L21/283 ,  H01L23/522 ,  H01L23/528

Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US20180130801A1

公开(公告)日：2018-05-10

申请号：US15577734

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Matthew V. Metz ,  Gilbert Dewey ,  Chandra S. Mohapatra ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Nadia M. Rahhal-Orabi ,  Tahir Ghani

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/8258

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L29/1054

Abstract: Non-silicon fin structures extend from a crystalline heteroepitaxial well material in a well recess of a substrate. III-V finFETs may be formed on the fin structures within the well recess while group IV finFETs are formed in a region of the substrate adjacent to the well recess. The well material may be electrically isolated from the substrate by an amorphous isolation material surrounding pillars passing through the isolation material that couple the well material to a seeding surface of the substrate and trap crystal growth defects. The pillars may be expanded over the well-isolation material by lateral epitaxial overgrowth, and the well recess filled with a single crystal of high quality. Well material may be planarized with adjacent substrate regions. N-type fin structures may be fabricated from the well material in succession with p-type fin structures fabricated from the substrate, or second epitaxial well.

公开(公告)号：US09935205B2

公开(公告)日：2018-04-03

申请号：US15335269

申请日：2016-10-26

Applicant: INTEL CORPORATION

Inventor： Seiyon Kim ,  Daniel A. Simon ,  Nadia M. Rahhal-Orabi ,  Chul-Hyun Lim ,  Kelin J. Kuhn

IPC: H01L29/775 ,  H01L29/786 ,  H01L27/088 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L29/161 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8238 ,  B82Y10/00 ,  H01L27/092 ,  H01L29/165

CPC classification number: H01L29/78696 ,  B82Y10/00 ,  H01L21/02603 ,  H01L21/823807 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78684

Abstract: A nanowire transistor of the present description may be produced with internal spacers formed by using sacrificial spacers during the fabrication thereof. Once the nanowire transistor is formed, the sacrificial spacers, which are position between the transistor gate and the source and drains (respectively), may be removed. The sacrificial material between channel nanowires of the nanowire transistor may then be removed and a dielectric material may be deposited to fill the spaces between the channel nanowires. The dielectric material not between the channel nanowires may be removed to form the internal spacers. External spacers, which are position between the transistor gate and the source and drains (respectively), may then be formed adjacent the internal spacers and transistor channel nanowires.

公开(公告)号：US20170323955A1

公开(公告)日：2017-11-09

申请号：US15528743

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Matthew V. Metz ,  Chandra S. Mohapatra ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Nadia M. Rahhal-Orabi ,  Tahir Ghani ,  Glenn A. Glass

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L29/04 ,  H01L27/108 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/762 ,  H01L27/108 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66484 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696 ,  H01L2029/7858

Abstract: An includes an epitaxial sub-fin structure disposed on a substrate, wherein a first portion of the sub-fin structure is disposed within a portion of the substrate, and a second portion of the sub-fin structure is disposed adjacent a dielectric material. A fin device structure is disposed on the sub-fin structure, wherein the fin device structure comprises the epitaxial material. A liner is disposed between the second portion of the sub-fin structure and the dielectric material. Other embodiments are described herein.