公开(公告)号：US20240087971A1

公开(公告)日：2024-03-14

申请号：US17943915

申请日：2022-09-13

申请人： Intel Corporation

发明人： Brandon C. MARIN ,  Gang DUAN ,  Srinivas V. PIETAMBARAM ,  Kristof DARMAWIKARTA ,  Jeremy D. ECTON ,  Suddhasattwa NAD ,  Hiroki TANAKA ,  Pooya TADAYON

IPC分类号： H01L23/15 ,  H01L23/00 ,  H01L23/538

CPC分类号： H01L23/15 ,  H01L23/5381 ,  H01L23/5384 ,  H01L24/16 ,  H01L2224/16225

摘要： Embodiments disclosed herein include interposers and methods of forming interposers. In an embodiment, an interposer comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass. In an embodiment, the interposer further comprises a cavity into the first surface of the substrate, a via through the substrate below the cavity, a first pad in the cavity over the via, and a second pad on the second surface of the substrate under the via.

公开(公告)号：US20240038722A1

公开(公告)日：2024-02-01

申请号：US18378978

申请日：2023-10-11

申请人： Intel Corporation

发明人： Mark T. BOHR ,  Wilfred GOMES ,  Rajesh KUMAR ,  Pooya TADAYON ,  Doug INGERLY

IPC分类号： H01L25/065 ,  H01L23/522 ,  H01L23/538 ,  H01L23/00

CPC分类号： H01L25/0655 ,  H01L23/5226 ,  H01L23/5384 ,  H01L24/13 ,  H01L2225/06541

摘要： Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

公开(公告)号：US20210392774A1

公开(公告)日：2021-12-16

申请号：US16902048

申请日：2020-06-15

申请人： Intel Corporation

发明人： Karumbu MEYYAPPAN ,  Kyle ARRINGTON ,  David CRAIG ,  Pooya TADAYON

IPC分类号： H05K7/14 ,  H05K7/20

摘要： Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate having a first surface and a second surface opposite from the first surface, and a die on the first surface of the package substrate. In an embodiment, the electronic package further comprises a socket interface on the second surface of the package substrate. In an embodiment, the socket interface comprises a first layer, wherein the first layer comprises a plurality of wells, a liquid metal within the plurality of wells, and a second layer over the plurality of wells.

公开(公告)号：US20210028087A1

公开(公告)日：2021-01-28

申请号：US16522443

申请日：2019-07-25

申请人： Intel Corporation

发明人： Shrenik KOTHARI ,  Chandra Mohan JHA ,  Weihau TANG ,  Robert SANKMAN ,  Xavier BRUN ,  Pooya TADAYON

IPC分类号： H01L23/42 ,  H01L23/367 ,  H01L23/373 ,  H01L23/522

摘要： Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.

公开(公告)号：US20200328139A1

公开(公告)日：2020-10-15

申请号：US16379619

申请日：2019-04-09

申请人： Intel Corporation

发明人： Chia-Pin CHIU ,  Robert SANKMAN ,  Pooya TADAYON

IPC分类号： H01L23/473 ,  H05K7/20 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373

摘要： Embodiments include semiconductor packages and cooling semiconductor packaging systems. A semiconductor package includes a second die on a package substrate, first dies on the second die, conductive bumps between the first dies and the second die, a cold plate and a manifold over the first dies, second die, and package substrate, and first openings in the manifold. The first openings are fluidly coupled through the conductive bumps. The semiconductor package may include a first fluid path through the first openings of the manifold, where a first fluid flows through the first fluid path. The semiconductor package may further include a second fluid path through second openings of the cold plate, where a second fluid flows through the second fluid path, and where the first and second fluids of the first and second fluid paths cool heat providing surfaces of the first dies, the second die, or the package substrate.

公开(公告)号：US20240244800A1

公开(公告)日：2024-07-18

申请号：US18290288

申请日：2021-09-24

申请人： Intel Corporation

发明人： Prabhakar SUBRAHMANYAM ,  Pooya TADAYON ,  Yi XIA ,  Ying-Feng PANG ,  Mark BIANCO

IPC分类号： H05K7/20

CPC分类号： H05K7/20809 ,  H05K7/20336 ,  H05K7/2039

摘要： An apparatus is described. The apparatus includes a chip package cooling assembly chamber having one or more features to receive one or more heat pipes that receive heat generated by one or more semiconductor devices that reside outside the chip package. In detail, the heat pipes that are thermally coupled to the VR FET heat sinks are attached to the outside of the cold plate (again, they can be screwed to the cold plate with a thermal interface material between them). Thus, heat generated by the VR FETs is transferred to the VR FET heatsinks and the chip package cold plate via the heat pipes. The heat is then transferred to the fluid while it runs through the cold plate and is removed from the system by the fluid as it exits the outlet.

公开(公告)号：US20240243099A1

公开(公告)日：2024-07-18

申请号：US18615654

申请日：2024-03-25

申请人： Intel Corporation

发明人： Mark T. BOHR ,  Wilfred GOMES ,  Rajesh KUMAR ,  Pooya TADAYON ,  Doug INGERLY

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538

CPC分类号： H01L25/0655 ,  H01L23/5226 ,  H01L23/5384 ,  H01L24/13 ,  H01L2225/06541

摘要： Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

公开(公告)号：US20240038729A1

公开(公告)日：2024-02-01

申请号：US18377639

申请日：2023-10-06

申请人： Intel Corporation

发明人： Pooya TADAYON

IPC分类号： H01L25/065 ,  H01L23/13 ,  H01L23/538

CPC分类号： H01L25/0657 ,  H01L25/0652 ,  H01L23/13 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/5386 ,  H01L2225/06589 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06558

摘要： Embodiments include a package substrate and semiconductor packages. A package substrate includes a first cavity in a top surface, first conductive pads on a first surface of the first cavity, a second cavity in a bottom surface, second conductive pads on a second surface of the second cavity, where the first surface is above the second surface, and a third cavity in the first and second cavities, where the third cavity vertically extends from the top surface to the bottom surface. The third cavity overlaps a first portion of the first cavity and a second portion of the second cavity. The package substrate may include conductive lines coupled to the first and second conductive pads, a first die in the first cavity, a second die in the second cavity, and interconnects in the third cavity that directly couple first die to the second die.

公开(公告)号：US20230260870A1

公开(公告)日：2023-08-17

申请号：US18137987

申请日：2023-04-21

申请人： Intel Corporation

发明人： Prabhakar SUBRAHMANYAM ,  Tewodros WONDIMU ,  Ying-Feng PANG ,  Muhammad AHMAD ,  Paul DIGLIO ,  David SHIA ,  Pooya TADAYON

IPC分类号： H01L23/427 ,  B05B1/14 ,  G01R31/26

CPC分类号： H01L23/427 ,  B05B1/14 ,  G01R31/2642

摘要： Embodiments disclosed herein include a thermal testing unit. In an embodiment, the thermal testing unit comprises a nozzle frame, and a nozzle plate within the frame. In an embodiment, the nozzle plate comprises a plurality of orifices through a thickness of the nozzle plate. In an embodiment, the thermal testing unit further comprises a housing attached to the nozzle plate.

公开(公告)号：US20220413240A1

公开(公告)日：2022-12-29

申请号：US17357941

申请日：2021-06-24

申请人： Intel Corporation

发明人： Srikant NEKKANTY ,  Pooya TADAYON ,  Wesley MORGAN ,  Tarek A. IBRAHIM ,  Sai VADLAMANI

IPC分类号： G02B6/42

摘要： Embodiments described herein may be related to apparatuses, processes, and techniques related to a cavity created in a package substrate, where the surface of the substrate at the bottom of the cavity, or alignment features at the surface of the substrate at the bottom of the cavity are used to accurately align a lens of a FAU to a lens of a PIC. In embodiments, the surface of the substrate at the bottom of the cavity has additional standoff pedestal features to aid in height tolerance control of the FAU to properly align the FAU lens when attached. Other embodiments may be described and/or claimed.