公开(公告)号：US20200258847A1

公开(公告)日：2020-08-13

申请号：US16274086

申请日：2019-02-12

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Gang DUAN ,  Deepak KULKARNI ,  Rahul MANEPALLI ,  Xiaoying GUO

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.

公开(公告)号：US20240250043A1

公开(公告)日：2024-07-25

申请号：US18606876

申请日：2024-03-15

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Gang DUAN ,  Deepak KULKARNI ,  Rahul MANEPALLI ,  Xiaoying GUO

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/3511

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.

公开(公告)号：US20210082852A1

公开(公告)日：2021-03-18

申请号：US16572354

申请日：2019-09-16

Applicant: Intel Corporation

Inventor： Bradon C. MARIN ,  Jung Kyu HAN ,  Thomas HEATON ,  Ali LEHAF ,  Rahul MANEPALLI ,  Srinivas PIETAMBARAM ,  Jacob VEHONSKY

IPC: H01L23/00 ,  C25D3/38 ,  C25D7/12 ,  C25D5/02

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to manufacturing a package having a substrate with a first side and a second side opposite the first side, where a copper layer is coupled with a first region of the first side of the substrate and includes a plurality of bumps coupled with the first region of the first side of the substrate where one or more second regions on the first side of the substrate not coupled with a copper layer, and where a layout of the one or more second regions on the first side of the substrate is to vary a growth, respectively, of each of the plurality of bumps during a plating process by modifying a local copper density of each of the plurality of bumps.

公开(公告)号：US20200315023A1

公开(公告)日：2020-10-01

申请号：US16363925

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Suddhasattwa NAD ,  Kassandra NIKKHAH ,  Joshua MICHALAK ,  Marcel WALL ,  Rahul MANEPALLI ,  Cemil GEYIK ,  Benjamin DUONG ,  Darko GRUJICIC

IPC: H05K3/10 ,  H01L23/538 ,  H05K1/11 ,  H01L23/498 ,  H01L21/48

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a first layer of a package substrate and a conductive trace over the first layer of the package substrate. In an embodiment, the conductive trace comprises a conductive body with a first surface over the first layer of the package substrate, a second surface opposite the first surface, and sidewall surfaces coupling the first surface to the second surface. In an embodiment, the second surface has a first roughness and the sidewall surfaces have a second roughness that is less than the first roughness.

公开(公告)号：US20200312665A1

公开(公告)日：2020-10-01

申请号：US16363688

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Suddhasattwa NAD ,  Jeremy ECTON ,  Bai NIE ,  Rahul MANEPALLI ,  Marcel WALL

IPC: H01L21/28 ,  H01L21/48 ,  H01L23/00

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a package substrate, a first die over the package substrate, the first die having a first bump pitch, a second die over the package substrate, the second die having a second bump pitch that is greater than the first bump pitch, and a plurality of conductive traces over the package substrate, the plurality of conductive traces electrically coupling the first die to the second die. In an embodiment, a first end region of the plurality of conductive traces proximate to the first die has a first line space (L/S) dimension, and a second end region of the plurality of conductive traces proximate to the second die has a second L/S dimension. In an embodiment, the second L/S dimension is greater than the first L/S dimension.

公开(公告)号：US20200251332A1

公开(公告)日：2020-08-06

申请号：US16269357

申请日：2019-02-06

Applicant: Intel Corporation

Inventor： Suddhasattwa NAD ,  Roy DITTLER ,  Darko GRUJICIC ,  Marcel WALL ,  Rahul MANEPALLI

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/285

Abstract: Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a self-assembled monolayer (SAM) layer over a first dielectric, where the SAM layer includes first end groups and second end groups. The second end groups may include a plurality of hydrophobic moieties. The package substrate also includes a conductive pad on the first dielectric, where the conductive pad has a bottom surface, a top surface, and a sidewall, and where the SAM layer surrounds and contacts a surface of the sidewall of the conductive pad. The hydrophobic moieties may include fluorinated moieties. The conductive pad includes a copper material, where the top surface of the conductive pad has a surface roughness that is approximately equal to a surface roughness of the as-plated copper material. The SAM layer may have a thickness that is approximately 0.1 nm to 20 nm.

公开(公告)号：US20200006232A1

公开(公告)日：2020-01-02

申请号：US16024707

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Rahul MANEPALLI ,  Gang DUAN

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.

公开(公告)号：US20240234225A1

公开(公告)日：2024-07-11

申请号：US18611534

申请日：2024-03-20

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Robert L. SANKMAN ,  Rahul MANEPALLI ,  Gang DUAN ,  Debendra MALLIK

IPC: H01L23/15 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L23/15 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/49827 ,  H01L23/5381

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a glass substrate, with a plurality of first pads on a first surface of the glass substrate, a plurality of second pads on a second surface of the glass substrate that is opposite from the first surface, a plurality of through glass vias (TGVs), wherein each TGV electrically couples a first pad to a second pad, wherein the plurality of first pads have a first pitch, and wherein the plurality of second pads have a second pitch that is greater than the first pitch, a bridge substrate over the glass substrate, a first die electrically coupled to first pads and the bridge substrate, and a second die electrically coupled to first pads and the bridge substrate, wherein the bridge substrate electrically couples the first die to the second die.

公开(公告)号：US20240088052A1

公开(公告)日：2024-03-14

申请号：US18513015

申请日：2023-11-17

Applicant: Intel Corporation

Inventor： Bai NIE ,  Gang DUAN ,  Srinivas PIETAMBARAM ,  Jesse JONES ,  Yosuke KANAOKA ,  Hongxia FENG ,  Dingying XU ,  Rahul MANEPALLI ,  Sameer PAITAL ,  Kristof DARMAWIKARTA ,  Yonggang LI ,  Meizi JIAO ,  Chong ZHANG ,  Matthew TINGEY ,  Jung Kyu HAN ,  Haobo CHEN

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/3511 ,  H01L2924/381

Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

公开(公告)号：US20240021523A1

公开(公告)日：2024-01-18

申请号：US18374576

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Rahul MANEPALLI ,  Gang DUAN

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L23/5384 ,  H01L21/565 ,  H01L23/3107 ,  H01L25/50 ,  H01L23/562 ,  H01L21/6835 ,  H01L23/5386 ,  H01L21/486 ,  H01L21/4853 ,  H01L25/0652 ,  H01L2221/68372 ,  H01L2225/06513 ,  H01L2225/06582 ,  H01L2225/06558 ,  H01L2225/06548 ,  H01L2225/06589

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.