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公开(公告)号:US10365708B2
公开(公告)日:2019-07-30
申请号:US15379283
申请日:2016-12-14
Applicant: Intel Corporation
Inventor: Simon N. Peffers , Sean M. Gulley , Thomas L. Dmukauskas , Aaron Gorius , Vinodh Gopal
IPC: G06F11/24 , G06F1/3296 , G01R31/28 , G06F1/324 , G06F1/3206
Abstract: Methods and apparatuses related to guardband recovery using in situ characterization are disclosed. In one example, a system includes a target circuit, a voltage regulator to provide a variable voltage to, a phase-locked loop (PLL) to provide a variable clock to, and a temperature sensor to sense a temperature of the target circuit, and a control circuit, wherein the control circuit is to set up a characterization environment by setting a temperature, voltage, clock frequency, and workload of the target circuit, execute a plurality of tests on the target circuit, when the target circuit passes the plurality of tests, adjust the variable voltage to increase a likelihood of the target circuit failing the plurality of tests and repeat the plurality of tests, and when the target circuit fails the plurality of tests, adjust the variable voltage to decrease a likelihood of the target circuit failing the plurality of tests.
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公开(公告)号:US11100483B2
公开(公告)日:2021-08-24
申请号:US15858097
申请日:2017-12-29
Applicant: Intel Corporation
Inventor: Ned M. Smith , Rajesh Poornachandran , Michael Nolan , Simon N. Peffers
IPC: G06Q40/04 , G06Q20/36 , G06Q40/06 , G06Q20/12 , H04L29/08 , H04L9/06 , G06N5/00 , G06Q20/06 , H04L9/32
Abstract: Systems and methods for exchanging digital content in an online layered hierarchical market and exchange network are disclosed. A Buyer utilizes one or more Curry functions that are relevant to content to be acquired thereby developing a Margin Future estimate for the received content. Each e-market layer in the hierarchy adds value to the content for use with one or more other e-market layers. Value is added by executing a Margin Function including a Curry function on the content, as defined in the Margin Future. An embodiment includes data, information, knowledge, and wisdom (DIKW) e-market layers. The Margin Future estimate may be recorded with an escrow agent acting as an intermediary with Investors. Once funded, the Buyer may acquire the content from the Seller and apply value added. Payment may be made when the value added content enters the e-market using electronic wallets. Other embodiments are described and claimed.
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公开(公告)号:US10985587B2
公开(公告)日:2021-04-20
申请号:US16057588
申请日:2018-08-07
Applicant: Intel Corporation
Inventor: Naoki Matsumura , Simon N. Peffers , Steven Lloyd , Michael T. Crocker , Aaron Gorius
IPC: H02J7/00
Abstract: In some examples, a control unit is configured to adjust charge termination voltage of a rechargeable energy storage device. The control unit is adapted to charge the rechargeable energy storage device to a charge termination voltage where the rechargeable energy storage device has capacity to support peak load but comes close to a system shutdown voltage after supporting peak load. The control unit is also adapted to increase the charge termination voltage if a voltage of the rechargeable energy storage device is near a system shutdown voltage after supporting peak load.
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14.
公开(公告)号:US10922079B2
公开(公告)日:2021-02-16
申请号:US15856245
申请日:2017-12-28
Applicant: Intel Corporation
Inventor: Vinodh Gopal , Kirk S. Yap , James Guilford , Simon N. Peffers
IPC: G06F9/00 , G06F9/30 , G06F16/2455 , G06F16/2453 , G06F16/245
Abstract: Data element filter logic (“hardware accelerator”) in a processor that offloads computation for an in-memory database select/extract operation from a Central Processing Unit (CPU) core in the processor is provided. The Data element filter logic provides a balanced performance across an entire range of widths (number of bits) of data elements in a column-oriented Database Management System.
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公开(公告)号:US20180164864A1
公开(公告)日:2018-06-14
申请号:US15379283
申请日:2016-12-14
Applicant: Intel Corporation
Inventor: Simon N. Peffers , Sean M. Gulley , Thomas L. Dmukauskas , Aaron Gorius , Vinodh Gopal
CPC classification number: G06F1/3296 , G01R31/2856 , G01R31/2874 , G01R31/2879 , G06F1/3206 , G06F1/324 , G06F11/24 , Y02D10/126 , Y02D10/172
Abstract: Methods and apparatuses related to guardband recovery using in situ characterization are disclosed. In one example, a system includes a target circuit, a voltage regulator to provide a variable voltage to, a phase-locked loop (PLL) to provide a variable clock to, and a temperature sensor to sense a temperature of the target circuit, and a control circuit, wherein the control circuit is to set up a characterization environment by setting a temperature, voltage, clock frequency, and workload of the target circuit, execute a plurality of tests on the target circuit, when the target circuit passes the plurality of tests, adjust the variable voltage to increase a likelihood of the target circuit failing the plurality of tests and repeat the plurality of tests, and when the target circuit fails the plurality of tests, adjust the variable voltage to decrease a likelihood of the target circuit failing the plurality of tests.
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公开(公告)号:US20180150471A1
公开(公告)日:2018-05-31
申请号:US15719774
申请日:2017-09-29
Applicant: Intel Corporation
Inventor: Vinodh Gopal , James D. Guilford , Kirk S. Yap , Simon N. Peffers , Daniel F. Cutter
CPC classification number: G06F3/0641 , G06F3/0604 , G06F3/0608 , G06F3/0611 , G06F3/0613 , G06F3/0617 , G06F3/0647 , G06F3/065 , G06F3/0653 , G06F3/067 , G06F7/06 , G06F8/65 , G06F8/654 , G06F8/656 , G06F8/658 , G06F9/3851 , G06F9/3891 , G06F9/4401 , G06F9/4881 , G06F9/5038 , G06F9/505 , G06F9/544 , G06F11/0709 , G06F11/0751 , G06F11/079 , G06F11/1453 , G06F11/3006 , G06F11/3034 , G06F11/3055 , G06F11/3409 , G06F12/023 , G06F12/0284 , G06F12/0692 , G06F13/1652 , G06F15/80 , G06F16/1744 , G06F21/57 , G06F21/6218 , G06F21/73 , G06F21/76 , G06F2212/401 , G06F2212/402 , G06F2221/2107 , G06T1/20 , G06T1/60 , G06T9/005 , H01R13/4538 , H01R13/631 , H03K19/1731 , H03M7/3084 , H03M7/40 , H03M7/42 , H03M7/60 , H03M7/6011 , H03M7/6017 , H03M7/6029 , H04L9/0822 , H04L12/2881 , H04L12/4633 , H04L41/044 , H04L41/046 , H04L41/0816 , H04L41/0853 , H04L41/0896 , H04L41/12 , H04L41/142 , H04L43/04 , H04L43/06 , H04L43/08 , H04L43/0894 , H04L47/20 , H04L47/2441 , H04L47/78 , H04L49/104 , H04L61/2007 , H04L63/1425 , H04L67/10 , H04L67/1014 , H04L67/327 , H04L67/36 , H05K7/1452 , H05K7/1487
Abstract: Technologies for database acceleration include a computing device having a database accelerator. The database accelerator performs a decompress operation on one or more compressed elements of a compressed database to generate one or more decompressed elements. After decompression of the compressed elements, the database accelerator prepares the one or more decompressed elements to generate one or more prepared elements to be processed by an accelerated filter. The database accelerator then performs the accelerated filter on the one or more prepared elements to generate one or more output elements. Other embodiments are described and claimed.
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17.
公开(公告)号:US11108406B2
公开(公告)日:2021-08-31
申请号:US16445556
申请日:2019-06-19
Applicant: Intel Corporation
Inventor: Simon N. Peffers , Vinodh Gopal , Kirk Yap
IPC: H03M7/38 , H03M7/30 , G06F12/0875 , G06F12/0888 , G06F9/54
Abstract: In one embodiment, an apparatus includes: a compression circuit to compress data blocks of one or more traffic classes; and a control circuit coupled to the compression circuit, where the control circuit is to enable the compression circuit to concurrently compress data blocks of a first traffic class and not to compress data blocks of a second traffic class. Other embodiments are described and claimed.
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公开(公告)号:US20190043050A1
公开(公告)日:2019-02-07
申请号:US16024676
申请日:2018-06-29
Applicant: INTEL CORPORATION
Inventor: Ned M. Smith , Rajesh Poornachandran , Michael Nolan , Simon N. Peffers
Abstract: In some examples, an apparatus uses a blockchain to agree on a time in an information exchange network. A first node includes a processor communicatively coupled to a storage device including instructions. When executed by the processor, the instructions cause the processor to verify a time estimate from each of one or more other node, to determine a time match of a time estimate of the first node with the time estimates from the one or more other node, and if the time match is determined, to commit to the blockchain a transaction that includes a time stamp.
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公开(公告)号:US09465237B2
公开(公告)日:2016-10-11
申请号:US14142591
申请日:2013-12-27
Applicant: Intel Corporation
Inventor: Larry R. Tate , Simon N. Peffers
Abstract: Embodiments are generally directed to automatic focus prescription lens eyeglasses. An embodiment of an apparatus includes one or more variable focus lenses coupled; one or more actuators to change the focus of the variable focus lenses; and one or more focus distance components coupled to detect a focus distance of one or more eyes of a user of the apparatus. The one or more actuators set a focal distance of each of the one or more variable focus lenses, a focal distance setting for each of the one or more variable focus lenses being determined in response to the focus distance of the one or both eyes of the user; and the focal distance setting for each of the one or more variable focus lenses includes adjustment for a vision prescription of the user.
Abstract translation: 实施例通常涉及自动聚焦处方镜片眼镜。 装置的实施例包括耦合的一个或多个可变焦距透镜; 一个或多个致动器来改变可变焦距透镜的焦点; 以及耦合以检测设备的用户的一个或多个眼睛的焦距的一个或多个焦距距离组件。 所述一个或多个致动器设置所述一个或多个可变焦距透镜中的每一个的焦距,所述一个或多个可变焦距透镜中的每一个的焦距设置响应于所述一个或多个可变焦距透镜的一个或两个眼睛的焦距而被确定 用户; 并且一个或多个可变焦距透镜中的每一个的焦距设置包括对用户的视觉处方的调整。
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