公开(公告)号：US20200373261A1

公开(公告)日：2020-11-26

申请号：US16421989

申请日：2019-05-24

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Jeremy D. ECTON ,  Aleksandar ALEKSOV ,  Kristof DARMAWIKARTA ,  Yonggang LI ,  Dilan SENEVIRATNE

IPC: H01L23/66 ,  H01P7/10 ,  H01P3/16 ,  H01L21/768 ,  H01P11/00 ,  H01L21/288

Abstract: A filter structure comprises a first dielectric buildup film. A second dielectric buildup film is over the first dielectric buildup film, the second dielectric buildup film including a metallization catalyst. A trench is in the second dielectric buildup film. A metal is selectively plated to sidewalls of the trench based at least in part on the metallization catalyst. A low-loss buildup film is over the metal that substantially fills the trench.

公开(公告)号：US20240188225A1

公开(公告)日：2024-06-06

申请号：US18060598

申请日：2022-12-01

Applicant: Intel Corporation

Inventor： Vinith BEJUGAM ,  Rengarajan SHANMUGAM ,  Srinivas PIETAMBARAM ,  Mao-Feng TSENG ,  Yonggang LI

IPC: H05K3/40 ,  C23C18/18 ,  C23C18/38 ,  H05K1/03 ,  H05K1/11 ,  H05K3/18

CPC classification number: H05K3/4038 ,  C23C18/1868 ,  C23C18/38 ,  H05K1/0306 ,  H05K1/115 ,  H05K3/181 ,  H05K2201/09563 ,  H05K2201/2081 ,  H05K2203/107

Abstract: A method for manufacturing a structured substrate is provided, the method including: forming a plurality of openings extending from a first surface of a substrate towards a second surface of the substrate, wherein the first surface is coplanar to the second surface, wherein the substrate comprises glass, and wherein each of the openings comprises a sidewall; forming a first layer at least on the sidewall of the openings; forming a second layer on the first layer, wherein the second layer comprises titanium; and depositing metal on the second layer to at least partially fill the openings.

公开(公告)号：US20230361002A1

公开(公告)日：2023-11-09

申请号：US17738085

申请日：2022-05-06

Applicant: Intel Corporation

Inventor： Vinith BEJUGAM ,  Kristof DARMAWIKARTA ,  Yonggang LI ,  Samuel GEORGE ,  Srinivas PIETAMBARAM

IPC: H01L23/48 ,  H01L23/15 ,  H01L21/48 ,  H01L21/68

CPC classification number: H01L23/481 ,  H01L23/15 ,  H01L21/486 ,  H01L21/68

Abstract: The present disclosure is directed to semiconductor dies and methods that provide a glass substrate, a pulsed laser tool to produce a line-shaped modification to the glass substrate for forming a plurality of structures in the glass substrate. The pulse laser tool may be provided with a predetermined pattern for its movement. The predetermined pattern moves the pulsed laser tool in a series of single steps in a first axial direction and in a series of plural lateral steps in a second axial direction that is perpendicular to the first axial direction, in particular, the single step is followed by the plural lateral steps in a repeating sequence. The series of plural lateral steps form an assembly of line-shaped modifications in parallel rows on the glass substrate, and thereafter the plurality of structures may be formed from the parallel rows of line-shaped modifications in the glass substrate.

公开(公告)号：US20200176272A1

公开(公告)日：2020-06-04

申请号：US16325100

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Vivek RAGHUNATHAN ,  Yonggang LI

IPC: H01L21/48 ,  H01L23/498

Abstract: Embodiments include methods for selective electroless plating of dielectric layers and devices formed by such processes. According to an embodiment, patterned surfaces are formed in a dielectric layer that includes metallic ceramic fillers. In some embodiments, the patterned surfaces form a line opening and a via opening that exposes a conductive pad. In an embodiment, the metallic ceramic fillers are activated to form activated surfaces over the patterned surfaces. A first metal is then deposited into the via opening with a first electroless solution that is a bottom-up deposition process. Thereafter, embodiments include forming a seed layer over exposed portions of the activated surfaces. In an embodiment, mid-gap states of the activated surfaces have an energy level approximately equal to a reduction potential of metal ions in a second electroless solution. Embodiments may then include depositing a second metal into the via opening with a third electroless solution.

公开(公告)号：US20200005990A1

公开(公告)日：2020-01-02

申请号：US16024721

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Sameer PAITAL ,  Srinivas PIETAMBARAM ,  Yonggang LI ,  Bai NIE ,  Kristof DARMAWIKARTA ,  Gang DUAN

IPC: H01F27/28 ,  H01F27/24 ,  H01L21/48 ,  H01L25/16 ,  H01L23/498 ,  H01F41/04 ,  H01L49/02

Abstract: Embodiments herein relate to systems, apparatuses, or processes for embedding a magnetic core or a magnetic inductor in a substrate layer by applying a copper layer to a portion of the substrate layer, creating a structure in the substrate layer on top of at least part of the copper layer to identify a defined region within the substrate layer, and inserting a magnetic paste into the defined region where the copper layer identifies a side of the defined region and where the structure is to contain the magnetic paste within the defined region while the magnetic paste cures.

公开(公告)号：US20180033707A1

公开(公告)日：2018-02-01

申请号：US15549970

申请日：2015-03-09

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Trina GHOSH DASTIDAR ,  Dilan SENEVIRATNE ,  Yonggang LI ,  Sirisha CHAVA

IPC: H01L23/14 ,  H05K3/10 ,  H05K3/18 ,  H05K3/06

CPC classification number: H01L23/14 ,  H01L21/4846 ,  H01L23/145 ,  H01L23/49822 ,  H01L23/49866 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K3/062 ,  H05K3/105 ,  H05K3/107 ,  H05K3/182 ,  H05K3/185 ,  H05K2201/0209 ,  H05K2203/107

Abstract: Embodiments of the present disclosure describe selective metallization of an integrated circuit (IC) substrate. In one embodiment, an integrated circuit (IC) substrate may include a dielectric material and metal crystals having a polyhedral shape dispersed in the dielectric material and bonded with a ligand that is to ablate when exposed to laser light such that the metal crystals having the ablated ligand are activated to provide a catalyst for selective electroless deposition of a metal. Other embodiments may be described and/or claimed