公开(公告)号：US20120199987A1

公开(公告)日：2012-08-09

申请号：US13450960

申请日：2012-04-19

申请人： Nishant Sinha ,  Krishna K. Parat

发明人： Nishant Sinha ,  Krishna K. Parat

IPC分类号： H01L23/488 ,  H01L21/50

CPC分类号： H01L27/11551 ,  H01L27/11524

摘要： Methods of forming semiconductor devices that include one or more arrays of memory devices in a three-dimensional arrangement, such as those that include forming a conductive contact in a dielectric material overlying a memory array, wherein a wafer bonding and cleaving process may be utilized to provide a foundation material for forming another memory array having an active region in electrical contact with the conductive contact. Additionally, the conductive contact may be formed in a donor wafer, which in turn may be bonded to a dielectric material overlying a memory array using another wafer bonding process. Novel semiconductor devices and structures including the same may be formed using such methods, for example.

摘要翻译： 形成包括三维布置的一个或多个存储器件阵列的半导体器件的方法，例如包括在覆盖存储器阵列的电介质材料中形成导电接触的方法，其中可利用晶片接合和切割工艺 提供用于形成具有与导电触点电接触的有源区的另一个存储器阵列的基础材料。 此外，导电接触可以形成在施主晶片中，该施主晶片又可以使用另一晶片接合工艺将其结合到覆盖存储器阵列的电介质材料上。 可以使用例如这样的方法形成包括其的新型半导体器件和结构。

公开(公告)号：US08178396B2

公开(公告)日：2012-05-15

申请号：US12402103

申请日：2009-03-11

申请人： Nishant Sinha ,  Krishna K. Parat

发明人： Nishant Sinha ,  Krishna K. Parat

IPC分类号： H01L21/82

CPC分类号： H01L27/11551 ,  H01L27/11524

摘要： Methods of forming semiconductor devices that include one or more arrays of memory devices in a three-dimensional arrangement, such as those that include forming a conductive contact in a dielectric material overlying a memory array, wherein a wafer bonding and cleaving process may be utilized to provide a foundation material for forming another memory array having an active region in electrical contact with the conductive contact. Additionally, the conductive contact may be formed in a donor wafer, which in turn may be bonded to a dielectric material overlying a memory array using another wafer bonding process. Novel semiconductor devices and structures including the same may be formed using such methods, for example.

摘要翻译： 形成包括三维布置的一个或多个存储器件阵列的半导体器件的方法，例如包括在覆盖存储器阵列的电介质材料中形成导电接触的方法，其中可利用晶片接合和切割工艺 提供用于形成具有与导电触点电接触的有源区的另一个存储器阵列的基础材料。 此外，导电接触可以形成在施主晶片中，该施主晶片又可以使用另一晶片接合工艺将其结合到覆盖存储器阵列的电介质材料上。 可以使用例如这样的方法形成包括其的新型半导体器件和结构。

公开(公告)号：US08945996B2

公开(公告)日：2015-02-03

申请号：US13085083

申请日：2011-04-12

申请人： Sanh D. Tang ,  Roger W. Lindsay ,  Krishna K. Parat

发明人： Sanh D. Tang ,  Roger W. Lindsay ,  Krishna K. Parat

IPC分类号： H01L23/52 ,  H01L21/82 ,  H01L27/10

CPC分类号： H01L27/11582 ,  G11C13/0007 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/75 ,  H01L23/52 ,  H01L23/528 ,  H01L27/10 ,  H01L27/101 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/249 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the horizontally elongated openings. Other aspects and implementations are disclosed.

摘要翻译： 形成电路部件的方法包括形成水平延伸和垂直重叠特征的堆叠。 堆叠具有主要部分和端部。 至少一些特征在末端部分中更深地移动到堆叠中的端部中在水平方向上延伸得更远。 操作结构通过主要部分的特征垂直地形成，并且虚拟结构通过端部中的特征垂直地形成。 通过特征形成水平细长的开口以从特征的材料形成水平细长的和垂直重叠的线。 这些线分别从主要部分延伸到端部，并且单独地横向地围绕操作结构和虚拟结构的垂直延伸部分的侧面。 至少部分地，在水平伸长的开口之间的主要端部和端部中部分地去除在线之间高度的牺牲材料。 公开了其他方面和实现。

公开(公告)号：US08624300B2

公开(公告)日：2014-01-07

申请号：US12969975

申请日：2010-12-16

申请人： Sanh D. Tang ,  John Zahurak ,  Shane Trapp ,  Krishna K. Parat

发明人： Sanh D. Tang ,  John Zahurak ,  Shane Trapp ,  Krishna K. Parat

IPC分类号： H01L23/52

CPC分类号： H01L21/8221 ,  H01L27/0688

摘要： Briefly, in accordance with one or more embodiments, multilayer memory device, comprising a lower deck and an upper deck disposed on the lower deck, the decks comprising one or more memory cells coupled via one or more contacts. An isolation layer is disposed between the upper deck, and one or more contacts are formed between the upper deck and the lower deck to couple one or more of the contact lines of the upper deck with one or more contact lines of the lower deck.

摘要翻译： 简而言之，根据一个或多个实施例，多层存储器设备包括设置在下层甲板上的下甲板和上甲板，甲板包括通过一个或多个触点耦合的一个或多个存储单元。 隔离层设置在上甲板之间，并且在上甲板和下甲板之间形成一个或多个触点，以将上甲板中的一个或多个接触线与下甲板的一个或多个接触线接合。

公开(公告)号：US08552568B2

公开(公告)日：2013-10-08

申请号：US13450960

申请日：2012-04-19

申请人： Nishant Sinha ,  Krishna K. Parat

发明人： Nishant Sinha ,  Krishna K. Parat

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L27/11551 ,  H01L27/11524

摘要： Methods of forming semiconductor devices that include one or more arrays of memory devices in a three-dimensional arrangement, such as those that include forming a conductive contact in a dielectric material overlying a memory array, wherein a wafer bonding and cleaving process may be utilized to provide a foundation material for forming another memory array having an active region in electrical contact with the conductive contact. Additionally, the conductive contact may be formed in a donor wafer, which in turn may be bonded to a dielectric material overlying a memory array using another wafer bonding process. Novel semiconductor devices and structures including the same may be formed using such methods.

摘要翻译： 形成包括三维布置的一个或多个存储器件阵列的半导体器件的方法，例如包括在覆盖存储器阵列的电介质材料中形成导电接触的方法，其中可利用晶片接合和切割工艺 提供用于形成具有与导电触点电接触的有源区的另一个存储器阵列的基础材料。 此外，导电接触可以形成在施主晶片中，该施主晶片又可以使用另一晶片接合工艺将其结合到覆盖存储器阵列的电介质材料上。 可以使用这种方法形成包括其的新型半导体器件和结构。

公开(公告)号：US08198172B2

公开(公告)日：2012-06-12

申请号：US12392742

申请日：2009-02-25

申请人： Gurtej S. Sandhu ,  Krishna K. Parat

发明人： Gurtej S. Sandhu ,  Krishna K. Parat

IPC分类号： H01L21/30

CPC分类号： H01L23/538 ,  H01L21/76254 ,  H01L21/78 ,  H01L21/8221 ,  H01L23/3185 ,  H01L25/043 ,  H01L25/0657 ,  H01L25/074 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

摘要： Methods for fabricating integrated circuit devices on an acceptor substrate devoid of circuitry are disclosed. Integrated circuit devices are formed by sequentially disposing one or more levels of semiconductor material on an acceptor substrate, and fabricating circuitry on each level of semiconductor material before disposition of a next-higher level. After encapsulation of the circuitry, the acceptor substrate is removed and semiconductor dice are singulated. Integrated circuit devices formed by the methods are also disclosed.

摘要翻译： 公开了在没有电路的受主基板上制造集成电路器件的方法。 集成电路器件通过在接受器衬底上依次布置一个或多个半导体材料层并且在配置下一较高电平之前在每个级别的半导体材料上制造电路而形成。 在封装电路之后，去除受主衬底并切割半导体晶片。 还公开了通过这些方法形成的集成电路器件。

公开(公告)号：US20100213578A1

公开(公告)日：2010-08-26

申请号：US12392742

申请日：2009-02-25

申请人： Gurtej S. Sandhu ,  Krishna K. Parat

发明人： Gurtej S. Sandhu ,  Krishna K. Parat

IPC分类号： H01L23/538 ,  H01L21/78

CPC分类号： H01L23/538 ,  H01L21/76254 ,  H01L21/78 ,  H01L21/8221 ,  H01L23/3185 ,  H01L25/043 ,  H01L25/0657 ,  H01L25/074 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

摘要： Methods for fabricating integrated circuit devices on an acceptor substrate devoid of circuitry are disclosed. Integrated circuit devices are formed by sequentially disposing one or more levels of semiconductor material on an acceptor substrate, and fabricating circuitry on each level of semiconductor material before disposition of a next-higher level. After encapsulation of the circuitry, the acceptor substrate is removed and semiconductor dice are singulated. Integrated circuit devices formed by the methods are also disclosed.

摘要翻译： 公开了在没有电路的受主基板上制造集成电路器件的方法。 集成电路器件通过在接受器衬底上依次布置一个或多个半导体材料层并且在配置下一较高电平之前在每个级别的半导体材料上制造电路而形成。 在封装电路之后，去除受主衬底并切割半导体晶片。 还公开了通过这些方法形成的集成电路器件。

公开(公告)号：US20150179267A1

公开(公告)日：2015-06-25

申请号：US14139219

申请日：2013-12-23

申请人： Charan Srinivasan ,  Pranav Kalavade ,  Shyam Sunder Raghunathan ,  Krishna K. Parat

发明人： Charan Srinivasan ,  Pranav Kalavade ,  Shyam Sunder Raghunathan ,  Krishna K. Parat

IPC分类号： G11C16/10 ,  G11C16/28

CPC分类号： G11C11/5642 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/28 ,  G11C16/3454

摘要： Embodiments of methods and systems disclosed herein provide a NAND cell programming technique that results in a substantially reduced Tprog to complete a programming operation. In particular, embodiments of the subject matter disclosed herein utilize two Vpgm programming pulses during each programming iteration, or loop. One of the two programming pulses corresponds to a conventional programming Vpgm pulse and the second pulse comprises a programming pulse that having a greater Vpgm that is greater than the conventional programming Vpgm so that the slow cells are programmed to PV in fewer pulses (iterations), thereby effectively simultaneously programming and verifying cells having different programming speeds.

摘要翻译： 本文公开的方法和系统的实施例提供NAND单元编程技术，其导致基本上减少的T程序以完成编程操作。 特别地，本文公开的主题的实施例在每个编程迭代期间利用两个Vpgm编程脉冲或循环。 两个编程脉冲之一对应于常规编程Vpgm脉冲，第二脉冲包括具有比常规编程Vpgm更大的Vpgm的编程脉冲，使得慢单元以更少的脉冲（迭代）被编程为PV， 从而有效地同时编程和验证具有不同编程速度的单元。

公开(公告)号：US20140380108A1

公开(公告)日：2014-12-25

申请号：US13977011

申请日：2012-03-29

申请人： Matthew Goldman ,  Krishna K. Parat ,  Pranav Kalavade ,  Nathan R. Franklin ,  Mark Helm

发明人： Matthew Goldman ,  Krishna K. Parat ,  Pranav Kalavade ,  Nathan R. Franklin ,  Mark Helm

IPC分类号： G11C29/50 ,  G06F11/10

CPC分类号： G11C29/50004 ,  G06F11/1048 ,  G06F11/1068 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/34 ,  G11C2029/0411 ,  G11C2029/5004

摘要： An apparatus may include a processor circuit a processor circuit to retrieve data from a non-volatile memory, and a multistrobe read module operable on the processor circuit to set a read operation to read a memory cell over a multiplicity of sense operations, where each sense operation is performed under a different sense condition. The multistrobe read module may be further operable to schedule a new sense operation to succeed a prior sense operation of the multiplicity of sense operations without recharge of the wordline when a value of one or more read condition is within a preset range. Other embodiments are disclosed and claimed.

摘要翻译： 一种装置可以包括处理器电路，用于从非易失性存储器检索数据，以及多处理器读取模块，其可在所述处理器电路上操作以设置读取操作以在多种感测操作上读取存储器单元， 在不同的感测条件下进行操作。 当一个或多个读取条件的值处于预设范围内时，该多画面读取模块还可以进一步操作，以调度新的感测操作，从而在许多感测操作的先前感测操作中继续进行，而不对字线进行再充电。 公开和要求保护其他实施例。

公开(公告)号：US20140252363A1

公开(公告)日：2014-09-11

申请号：US13786925

申请日：2013-03-06

申请人： Haitao Liu ,  Chandra V. Mouli ,  Krishna K. Parat ,  Jie Sun ,  Guangyu Huang

发明人： Haitao Liu ,  Chandra V. Mouli ,  Krishna K. Parat ,  Jie Sun ,  Guangyu Huang

IPC分类号： H01L27/088 ,  H01L21/8239

CPC分类号： H01L27/11582 ,  G11C16/06 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/16 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： A method to fabricate a three dimensional memory structure includes forming an array stack, creating a layer of sacrificial material above the array stack, etching a hole through the layer of sacrificial material and the array stack, creating a pillar of semiconductor material in the hole to form at least two vertically stacked flash memory cells that use the pillar as a common body, removing at least some of the layer of sacrificial material around the pillar to expose a portion of the pillar, and forming a field effect transistor (FET) using the portion of the pillar as the body of the FET.

摘要翻译： 制造三维存储器结构的方法包括形成阵列堆叠，在阵列堆叠上方产生牺牲材料层，蚀刻通过牺牲材料层和阵列堆叠的孔，在孔中产生半导体材料的柱 形成使用该柱作为共同体的至少两个垂直堆叠的闪存单元，去除柱周围的牺牲材料层中的至少一部分以暴露柱的一部分，以及使用该场效应晶体管 柱的一部分作为FET的主体。