公开(公告)号：US10199318B2

公开(公告)日：2019-02-05

申请号：US15481500

申请日：2017-04-07

Applicant: MEDIATEK INC.

Inventor： Nai-Wei Liu ,  Tzu-Hung Lin ,  I-Hsuan Peng ,  Che-Hung Kuo ,  Che-Ya Chou ,  Wei-Che Huang

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  H01L25/10

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure. The RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace. The RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The extended wing portion overlaps at least one-half of a boundary of the symmetrical portion when observed from a plan view.

公开(公告)号：US20180323127A1

公开(公告)日：2018-11-08

申请号：US15968449

申请日：2018-05-01

Applicant: MediaTek Inc.

Inventor： Nai-Wei Liu ,  Tzu-Hung Lin ,  I-Hsuan Peng ,  Ching-Wen Hsiao ,  Wei-Che Huang

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/538

Abstract: A semiconductor package structure is provided. The structure includes a first semiconductor die having a first surface and a second surface opposite thereto. A first molding compound surrounds the first semiconductor die. A first redistribution layer (RDL) structure is disposed on the second surface of the first semiconductor die and laterally extends on the first molding compound. A second semiconductor die is disposed on the first RDL structure and has a first surface and a second surface opposite thereto. A second molding compound surrounds the second semiconductor die. A first protective layer covers a sidewall of the first RDL structure and a sidewall of the first molding compound.

公开(公告)号：US20180102343A1

公开(公告)日：2018-04-12

申请号：US15644849

申请日：2017-07-10

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung Lin ,  I-Hsuan Peng ,  Nai-Wei Liu ,  Wei-Che Huang

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L25/0655 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L29/0657 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/24137 ,  H01L2224/94 ,  H01L2924/10155 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2224/214

Abstract: A semiconductor chip package includes a first die and a second die. The first die and second die are coplanar and disposed in proximity to each other in a side-by-side fashion. A non-straight line shaped interface gap is disposed between the first die and second die. A molding compound surrounds the first die and second die. A redistribution layer (RDL) structure is disposed on the first die, the second die and on the molding compound. The first semiconductor die is electrically connected to the second semiconductor die through the RDL structure.

公开(公告)号：US20170053884A1

公开(公告)日：2017-02-23

申请号：US15182581

申请日：2016-06-14

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung Lin ,  Ching-Wen Hsiao ,  I-Hsuan Peng ,  Nai-Wei Liu

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/31

CPC classification number: H01L24/14 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/14134 ,  H01L2224/14153 ,  H01L2224/14177 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/18162 ,  H01L2924/19102 ,  H01L2924/381 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A ball grid array for an integrated circuit package includes an array of connection points derived from a base unit of hexagonal pattern repeated in at least one or more sections of the integrated circuit package. According to one embodiment, the connection points are solder balls mounted on a lower surface of the integrated circuit package.

Abstract translation: 用于集成电路封装的球栅阵列包括源自在集成电路封装的至少一个或多个部分中重复的六边形图案的基本单元的连接点阵列。 根据一个实施例，连接点是安装在集成电路封装的下表面上的焊球。

公开(公告)号：US11854784B2

公开(公告)日：2023-12-26

申请号：US17989498

申请日：2022-11-17

Applicant: MediaTek Inc.

Inventor： Yen-Yao Chi ,  Nai-Wei Liu ,  Ta-Jen Yu ,  Tzu-Hung Lin ,  Wen-Sung Hsu ,  Shih-Chin Lin

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/29

CPC classification number: H01L23/3114 ,  H01L21/561 ,  H01L21/568 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/024 ,  H01L2224/02331 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/12105 ,  H01L2224/13024

Abstract: A semiconductor package structure includes a semiconductor die, a redistribution layer (RDL) structure, a protective insulating layer, and a conductive structure. The semiconductor die has a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. The RDL structure is on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The protective insulating layer covers the RDL structure, the second surface and the third surface of the semiconductor die. The conductive structure passes through the protective insulating layer and is electrically coupled to the RDL structure.

公开(公告)号：US11688655B2

公开(公告)日：2023-06-27

申请号：US17182525

申请日：2021-02-23

Applicant: MEDIATEK INC.

Inventor： Chia-Cheng Chang ,  Tzu-Hung Lin ,  I-Hsuan Peng ,  Nai-Wei Liu

IPC: H01L23/053 ,  H01L23/16 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16 ,  H01L23/00 ,  H01L25/065 ,  H01L23/04 ,  H01L25/18 ,  H01L23/433 ,  H01L23/373

CPC classification number: H01L23/053 ,  H01L23/04 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/24 ,  H01L25/0655 ,  H01L25/165 ,  H01L25/18 ,  H01L23/367 ,  H01L23/3737 ,  H01L23/4334 ,  H01L2224/24137 ,  H01L2924/19105 ,  H01L2924/3511

Abstract: A semiconductor package structure including a package substrate, at least one semiconductor die, a lid structure, a first electronic component and a heat sink is provided. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is on the first surface of the package substrate and is surrounded by an encapsulating layer. The lid structure surrounds and is spaced apart from the encapsulating layer. The lid structure includes a first opening that is covered by the first surface of the package substrate. The first electronic component is over the first surface of the package substrate and arranged within the first opening of the lid structure. The heat sink covers the lid structure and the semiconductor die.

公开(公告)号：US11652273B2

公开(公告)日：2023-05-16

申请号：US17676102

申请日：2022-02-18

Applicant: MediaTek Inc.

Inventor： Nai-Wei Liu ,  Yen-Yao Chi ,  Yeh-Chun Kao ,  Shih-Huang Yeh ,  Tzu-Hung Lin ,  Wen-Sung Hsu

IPC: H01Q1/22 ,  H01Q1/38 ,  H01L23/00 ,  H01L23/538 ,  H01L23/66 ,  H01Q9/28 ,  H01L23/31

CPC classification number: H01Q1/2283 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/20 ,  H01Q1/38 ,  H01Q9/285 ,  H01L23/3128 ,  H01L2223/6677 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2924/01029

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a redistribution layer (RDL) structure formed on a non-active surface of a semiconductor die. An antenna structure includes a first antenna element formed in the RDL structure, a first insulating layer covering the RDL structure, a second insulating layer formed on the first insulating layer, and a second antenna element formed on and in direct contact with the second insulating layer.

公开(公告)号：US11574881B2

公开(公告)日：2023-02-07

申请号：US17361285

申请日：2021-06-28

Applicant: MediaTek Inc.

Inventor： Nai-Wei Liu ,  Yen-Yao Chi ,  Yeh-Chun Kao ,  Shih-Huang Yeh ,  Tzu-Hung Lin ,  Wen-Sung Hsu

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01Q1/22 ,  H01Q9/04 ,  H01Q9/16 ,  H01L23/552 ,  H01Q1/52

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first redistribution layer (RDL) structure formed on a non-active surface of a semiconductor die. A second RDL structure is formed on and electrically coupled to an active surface of the semiconductor die. A ground layer is formed in the first RDL structure. A first molding compound layer is formed on the first RDL structure. A first antenna includes a first antenna element formed in the second RDL structure and a second antenna element formed on the first molding compound layer. Each of the first antenna element and the second antenna element has a first portion overlapping the semiconductor die as viewed from a top-view perspective.

公开(公告)号：US11450606B2

公开(公告)日：2022-09-20

申请号：US16430076

申请日：2019-06-03

Applicant: MediaTek Inc.

Inventor： Yen-Yao Chi ,  Nai-Wei Liu ,  Tzu-Hung Lin ,  Ta-Jen Yu ,  Wen-Sung Hsu

IPC: H01L23/40 ,  H01L23/528 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package structure including a semiconductor die having a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. A first protective insulating layer covers the first and third surfaces of the semiconductor die. A redistribution layer (RDL) structure is electrically coupled to the semiconductor die and surrounded by the first protective insulating layer on the first surface of the semiconductor die. A first passivation layer covers the first protective insulating layer and the RDL structure. At least one conductive structure passes through the first passivation layer and is electrically coupled to the RDL structure. A method of forming the semiconductor package is also provided.

公开(公告)号：US10784211B2

公开(公告)日：2020-09-22

申请号：US15906098

申请日：2018-02-27

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung Lin ,  Chia-Cheng Chang ,  I-Hsuan Peng ,  Nai-Wei Liu

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L23/043 ,  H01L23/13 ,  H01L23/538

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate having a first surface and a second surface opposite thereto. The substrate includes a wiring structure. The semiconductor package structure also includes a first semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure. The semiconductor package structure further includes a second semiconductor die disposed over the first surface of the substrate and electrically coupled to the wiring structure. The first semiconductor die and the second semiconductor die are separated by a molding material. In addition, the semiconductor package structure includes a first hole and a second hole formed on the second surface of the substrate.