SEMICONDUCTOR PACKAGE ASSEMBLY
    11.
    发明申请

    公开(公告)号:US20230046413A1

    公开(公告)日:2023-02-16

    申请号:US17812786

    申请日:2022-07-15

    Applicant: MEDIATEK INC.

    Abstract: A semiconductor assembly package is provided. The semiconductor package assembly includes a system-on-chip (SOC) package, a memory package and a heat spreader. The SOC package includes a logic die and a first substrate. The logic die has pads on it. The first substrate is electrically connected to the logic die by the pads. The memory package includes a second substrate and a memory die. The second substrate has a top surface and a bottom surface. The memory die is mounted on the top surface of the second substrate and is electrically connected to the second substrate using bonding wires. The heat spreader is disposed between the SOC package and the memory package, wherein the heat spreader is in contact with a back surface of the logic die away from the pads.

    SEMICONDUCTOR PACKAGE STRUCTURE
    13.
    发明申请

    公开(公告)号:US20210159177A1

    公开(公告)日:2021-05-27

    申请号:US17098659

    申请日:2020-11-16

    Applicant: MEDIATEK INC.

    Abstract: A semiconductor package structure includes a substrate, a bridge structure, a redistribution layer, a first semiconductor component, and a second semiconductor component. The substrate has a wiring structure. The bridge structure is over the substrate. The redistribution layer is over the bridge structure. The first semiconductor component and the second semiconductor component are over the redistribution layer, wherein the first semiconductor component is electrically coupled to the second semiconductor component through the redistribution layer and the bridge structure.

    CHIP SCALE PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME

    公开(公告)号:US20200312732A1

    公开(公告)日:2020-10-01

    申请号:US16903458

    申请日:2020-06-17

    Applicant: MEDIATEK INC.

    Abstract: A semiconductor package structure includes a semiconductor die, a redistribution layer (RDL) structure, a protective insulating layer, and a conductive structure. The semiconductor die has a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. The RDL structure is on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The protective insulating layer covers the RDL structure, the second surface and the third surface of the semiconductor die. The conductive structure passes through the protective insulating layer and is electrically coupled to the RDL structure.

    SEMICONDUCTOR PACKAGE
    19.
    发明公开

    公开(公告)号:US20230387075A1

    公开(公告)日:2023-11-30

    申请号:US18303693

    申请日:2023-04-20

    Applicant: MEDIATEK INC.

    Abstract: A semiconductor package includes an interposer over a substrate that includes interconnect traces, a redistribution structure on the interposer, a first semiconductor structure, a second semiconductor structure and a third semiconductor structure on the redistribution structure. The first semiconductor structure includes a first semiconductor die and a first encapsulant that encapsulates the first semiconductor die. The second semiconductor structure includes a second semiconductor die and a second encapsulant that encapsulates the second semiconductor die. The third semiconductor structure is disposed adjacent to a corner or an edge of the substrate in a top plan view of the substrate. The third semiconductor structure includes a third semiconductor die and a third encapsulant that encapsulates the third semiconductor die. The third semiconductor structure is electrically insulated from the substrate, the first semiconductor structure and the second semiconductor structure.

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