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    CONFIGURABLE TIME DELAYS FOR EQUALIZING PULSE WIDTH MODULATION TIMING
    11.
    发明申请
    CONFIGURABLE TIME DELAYS FOR EQUALIZING PULSE WIDTH MODULATION TIMING 有权
    用于均衡脉冲宽度调制时序的可配置时间延迟

    公开(公告)号：US20140240020A1

    公开(公告)日：2014-08-28

    申请号：US13778436

    申请日：2013-02-27

    Applicant: MICROCHIP TECHNOLOGY INCORPORATED

    Inventor： Bryan Kris ,  John Day ,  Alex Dumais ,  Stephen Bowling

    IPC: H03K5/13

    CPC classification number: H03K5/133 ,  H02M1/08 ,  H02M1/32 ,  H02M1/38 ,  H02M3/3353 ,  H02M3/33576

    Abstract: A plurality of PWM generators have user configurable time delay circuits for each PWM control signal generated therefrom. The time delay circuits are adjusted so that each of the PWM control signals arrive at their associated power transistors at the same time. This may be accomplished by determining a maximum delay time of the PWM control signal that has to traverse the longest propagation time and then setting the delay for that PWM control signal to substantially zero delay. Thereafter, all other delay time settings for the other PWM control signals may be determined by subtracting the propagation time for each of the other PWM control signals from the longest propagation time. Thereby insuring that all of the PWM control signals arrive at their respective power transistor control nodes with substantially the same time relationships as when they left their respective PWM generators.

    Abstract translation: 多个PWM发生器具有用于由其产生的每个PWM控制信号的用户可配置的时间延迟电路。 时间延迟电路被调整，使得每个PWM控制信号同时到达它们相关联的功率晶体管。 这可以通过确定必须经过最长传播时间的PWM控制信号的最大延迟时间，然后将该PWM控制信号的延迟设定为基本为零的延迟来实现。 此后，可以通过从最长传播时间减去每个其它PWM控制信号的传播时间来确定其它PWM控制信号的所有其他延迟时间设置。 从而确保所有的PWM控制信号到达它们各自的功率晶体管控制节点时具有与其离开它们各自的PWM发生器时基本相同的时间关系。

    PULSE WIDTH MODULATION LOAD SHARE BUS
    12.
    发明申请
    PULSE WIDTH MODULATION LOAD SHARE BUS 有权
    脉冲宽度调制负载分配总线

    公开(公告)号：US20140229755A1

    公开(公告)日：2014-08-14

    申请号：US13764423

    申请日：2013-02-11

    Applicant: MICROCHIP TECHNOLOGY INCORPORATED

    Inventor： Bryan Kris

    IPC: G06F1/32

    CPC classification number: H02M3/1584 ,  G06F1/263 ,  H02J1/102

    Abstract: Power supply modules have outputs coupled in parallel and convey load share balancing information over a single wire load share bus. Pulse width modulation (PWM) signals represent output loading of each of the power supply modules over the single wire load share bus. The PWM load share signal width (time asserted) of the PWM signal represents the output loading of the respective power supply module. Each of the power supply modules detect the assertion of the PWM signal on the load share bus and then each of them simultaneously drive the load share bus with a PWM signal representing their respective output loading. The power supply module having the greatest percent loading will assert its PWM load share signal longest, and the other power supply modules will thereafter adjust their outputs to more evenly supply power outputs to the load.

    Abstract translation: 电源模块具有并联耦合的输出，并通过单个有线负载共享总线传送负载共享平衡信息。 脉宽调制（PWM）信号表示单线负载共享总线上每个电源模块的输出负载。 PWM信号的PWM负载共享信号宽度（时间有效）表示相应电源模块的输出负载。 每个电源模块检测负载共享总线上的PWM信号的断言，然后它们每个都以表示其相应输出负载的PWM信号同时驱动负载共享总线。 具有最大负载百分比的电源模块将使其PWM负载共享信号最长，其他电源模块此后会调整其输出以更均匀地向负载提供电源输出。

    Microcontroller with average current measurement circuit using voltage-to-current converters
    16.
    发明授权
    Microcontroller with average current measurement circuit using voltage-to-current converters 有权

    公开(公告)号：US10044264B2

    公开(公告)日：2018-08-07

    申请号：US15157879

    申请日：2016-05-18

    Applicant: Microchip Technology Incorporated

    Inventor： Bryan Kris ,  James Bartling

    IPC: G05F1/56 ,  H02M3/156 ,  G01R19/00 ,  G01R19/255 ,  H02M1/08 ,  H03F3/45 ,  H03G3/20 ,  H03M1/12 ,  H02M1/00

    Abstract: The average of a complex waveform measured over a time period may be determined by first converting the complex waveform to a voltage, then converting this voltage to a current and using this current to charge a capacitor. At the end of the measurement time period the voltage charge (sample voltage) on the capacitor may be sampled by a sample and hold circuit associated with an analog-to-digital converter (ADC). Then the voltage charge on the sample capacitor may be removed, e.g., capacitor plates shorted by a dump switch in preparation for the next average of the complex waveform sample measurement cycle. The ADC then converts this sampled voltage charge to a digital representation thereof and a true average of the complex waveform may be determined, e.g., calculated therefrom in combination with the measurement time period.

    ADC controller With Temporal Separation
    17.
    发明申请
    ADC controller With Temporal Separation 审中-公开

    公开(公告)号：US20180054209A1

    公开(公告)日：2018-02-22

    申请号：US15677909

    申请日：2017-08-15

    Applicant: Microchip Technology Incorporated

    Inventor： Bryan Kris

    IPC: H03M1/08 ,  H03M1/60 ,  H03M1/12 ,  H03M1/10 ,  H02J7/00

    CPC classification number: H03M1/0827 ,  H02J7/0055 ,  H02J7/0077 ,  H03M1/1028 ,  H03M1/1215 ,  H03M1/1225 ,  H03M1/60

    Abstract: Embodiments of the present disclosure may include an ADC circuit including channel register sets, a conversion request flip-flop, a priority encoder circuit, and a controller circuit. The controller circuit may be configured to receive a conversion request signal, latch the conversion request signal into the conversion request flip-flop, determine by the priority encoder circuit a highest priority pending conversion request, and output an active channel identifier code. The channel identifier code may be configured to select the data channel register sets that are active by identifying received selection bits. The embodiments may include logic to store a converted value from a selected analog input to a data output register based on the channel identifier code.

    Configurable Mailbox Data Buffer Apparatus
    19.
    发明申请
    Configurable Mailbox Data Buffer Apparatus 审中-公开
    可配置邮箱数据缓冲设备

    公开(公告)号：US20160371200A1

    公开(公告)日：2016-12-22

    申请号：US15184789

    申请日：2016-06-16

    Applicant: Microchip Technology Incorporated

    Inventor： Michael Catherwood ,  David Mickey ,  Bryan Kris

    IPC: G06F13/10 ,  G06F13/20 ,  G06F13/42 ,  G06F13/16

    CPC classification number: G06F13/102 ,  G06F13/16 ,  G06F13/20 ,  G06F13/42 ,  G06F15/167

    Abstract: A single chip microcontroller has a master core and at least one slave core. The master core is clocked by a master system clock and the slave core is clocked by a slave system clock and wherein each core is associated with a plurality of peripheral devices to form a master microcontroller and a slave microcontroller, respectively. A communication interface is provided between the master microcontroller and the slave microcontroller, wherein the communication interface has a plurality of configurable directional data registers coupled with a flow control logic which is configurable to assign a direction to each of the plurality of configurable data registers.

    Abstract translation: 单片微控制器具有主核和至少一个从核。 主核心由主系统时钟计时，从核心由从系统时钟计时，并且其中每个核心分别与多个外围设备相关联以形成主微控制器和从微控制器。 在主微控制器和从属微控制器之间提供通信接口，其中通信接口具有多个可配置方向性数据寄存器，与流控制逻辑耦合，流控制逻辑可配置为向多个可配置数据寄存器中的每一个分配方向。

    Central Processing Unit With Enhanced Instruction Set
    20.
    发明申请
    Central Processing Unit With Enhanced Instruction Set 审中-公开
    具有增强指令集的中央处理单元

    公开(公告)号：US20160321202A1

    公开(公告)日：2016-11-03

    申请号：US15141823

    申请日：2016-04-29

    Applicant: Microchip Technology Incorporated

    Inventor： Michael Catherwood ,  David Mickey ,  Bryan Kris ,  Calum Wilkie ,  Jason Sachs ,  Andreas Reiter

    IPC: G06F13/16 ,  G06F13/40 ,  G06F12/14

    CPC classification number: G06F13/1673 ,  G06F9/30043 ,  G06F9/3877 ,  G06F9/3879 ,  G06F12/14 ,  G06F13/4068 ,  G06F2212/1052

    Abstract: An integrated circuit has a master processing core with a central processing unit coupled with a non-volatile memory and a slave processing core operating independently from the master processing core and having a central processing unit coupled with volatile program memory, wherein the master central processing unit is configured to transfer program instructions into the non-volatile memory of the slave processing core and wherein a transfer of the program instructions is performed by executing a dedicated instruction within the central processing unit of the master processing core.

    Abstract translation: 集成电路具有主处理核心，其具有与非易失性存储器耦合的中央处理单元和独立于主处理核心并具有与易失性程序存储器耦合的中央处理单元操作的从属处理核心，其中主中央处理单元 被配置为将程序指令传送到从处理核心的非易失性存储器，并且其中通过在主处理核心的中央处理单元内执行专用指令来执行程序指令的传送。

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