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    Pre-compensation of memory threshold voltage
    13.
    发明授权
    Pre-compensation of memory threshold voltage 有权
    内存阈值电压预补偿

    公开(公告)号：US09589659B1

    公开(公告)日：2017-03-07

    申请号：US15164171

    申请日：2016-05-25

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Tommaso Vali ,  Andrea D'Alessandro ,  Violante Moschiano ,  Mattia Cichocki ,  Michele Incarnati ,  Federica Paolini

    IPC: G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G11C16/10 ,  G11C16/26 ,  G11C16/14

    CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3427 ,  G11C2211/5621 ,  G11C2211/5648

    Abstract: Methods of operating a memory include storing a first target data state of multiple possible data states of a first memory cell to be programmed in a target data latch coupled to a data node, storing at least one bit of a second target data state of the multiple possible data states of a second memory cell to be programmed in an aggressor data latch coupled to the data node, and programming the first memory cell and performing a program verify operation for the first target data state to determine if the first memory cell is verified for the first target data state. The program verify operation including: an intermediate verify corresponding to an amount of aggression to apply a voltage to the data node when performing the intermediate verify, based on the at least one bit of the second target state stored in the aggressor data latch; and a program verify corresponding to a condition of no aggression to apply to the voltage to the data node when performing the program verify, based on the at least one bit of the second target state stored in the aggressor data latch. The methods including inhibiting the first memory cell from further programming if the first memory cell is verified during the intermediate verify and the at least one bit in the aggressor data latch corresponds to the particular amount of aggression, or the first memory cell is verified during the program verify and the at least one bit in the aggressor data latch corresponds to the condition of no aggression. The second memory cell is a neighbor of the first memory cell.

    Abstract translation: 操作存储器的方法包括将要编程的第一存储器单元的多个可能数据状态的第一目标数据状态存储在耦合到数据节点的目标数据锁存器中，存储多个第二目标数据状态的至少一位 要在与数据节点耦合的攻击者数据锁存器中编程的第二存储器单元的可能数据状态，以及编程第一存储器单元并对第一目标数据状态执行程序验证操作，以确定第一存储器单元是否被验证 第一个目标数据状态。 所述程序验证操作包括：基于存储在所述侵入者数据锁存器中的所述第二目标状态的所述至少一个位，执行所述中间验证时，对应于所述攻击量的中间验证以向所述数据节点施加电压; 以及基于存储在侵略者数据锁存器中的第二目标状态的至少一个位，在执行程序验证时，对应于不侵略条件的程序验证应用于数据节点的电压。 所述方法包括如果在中间验证期间验证第一存储器单元并且侵略者数据锁存器中的至少一个位对应于特定的侵略量，则禁止第一存储器单元进一步编程，或者在第一存储器单元期间验证第一存储器单元 程序验证，并且攻击者数据锁存中的至少一个位对应于无侵略的条件。 第二存储器单元是第一存储器单元的邻居。

    BITLINE DRIVER ISOLATION FROM PAGE BUFFER CIRCUITRY IN MEMORY DEVICE
    17.
    发明申请
    BITLINE DRIVER ISOLATION FROM PAGE BUFFER CIRCUITRY IN MEMORY DEVICE 有权

    公开(公告)号：US20220020435A1

    公开(公告)日：2022-01-20

    申请号：US16947091

    申请日：2020-07-17

    Applicant: Micron Technology, Inc.

    Inventor： Violante Moschiano ,  Dheeraj Srinivasan ,  Andrea D'Alessandro

    IPC: G11C16/24 ,  G11C16/26 ,  G11C16/04

    Abstract: A page buffer circuit in a memory device includes a logic element configured to perform a series of calculations pertaining to one or more memory access operations and generate a plurality of calculation results associated with the series of calculations and a dynamic memory element coupled with the logic element and configured to store the plurality of calculation results. The page buffer circuit further includes an isolation element coupled between the logic element and the dynamic memory element, the isolation element to permit a calculation result from the logic element to pass to the dynamic memory element when activated and one or more bitline driver circuits coupled to the dynamic memory element and configured to perform pre-charging operations associated with the one or more memory access operations and based at least in part on the plurality of calculation results stored in the dynamic memory element. The one or more bitline driver circuits can perform a first pre-charging operation on the memory array based at least in part on a first calculation result stored in the dynamic memory element during a first period of time when the isolation element is deactivated to disconnect the logic element from the dynamic memory element, and the logic element is configured to concurrently generate a second calculation result during the first period of time.

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