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公开(公告)号：US20180366203A1
公开(公告)日：2018-12-20
申请号：US16111319
申请日：2018-08-24
发明人： Luyen Vu , Kalyan C. Kavalipurau , Jae-Kwan Park , Erwin E. Yu
摘要： Apparatus and methods to vary, in response to temperature, a precharge voltage level of a sense node during a sense operation, a sense node develop time during the sense operation, and/or a ratio of a deboost voltage level capacitively decoupled from the sense node to a boost voltage level capacitively coupled to the sense node during the sense operation.
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公开(公告)号：US10127988B2
公开(公告)日：2018-11-13
申请号：US15248692
申请日：2016-08-26
发明人： Luyen Vu , Kalyan C. Kavalipurau , Jae-Kwan Park , Erwin E. Yu
摘要： Sense circuits and methods to vary, in response to temperature, a precharge voltage level of a sense node during a sense operation, a sense node develop time during the sense operation, and/or a ratio of a deboost voltage level capacitively decoupled from the sense node to a boost voltage level capacitively coupled to the sense node during the sense operation.
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公开(公告)号：US20180061497A1
公开(公告)日：2018-03-01
申请号：US15248692
申请日：2016-08-26
发明人： Luyen Vu , Kalyan C. Kavalipurau , Jae-Kwan Park , Erwin E. Yu
摘要： Sense circuits and methods to vary, in response to temperature, a precharge voltage level of a sense node during a sense operation, a sense node develop time during the sense operation, and/or a ratio of a deboost voltage level capacitively decoupled from the sense node to a boost voltage level capacitively coupled to the sense node during the sense operation.
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公开(公告)号：US12068037B2
公开(公告)日：2024-08-20
申请号：US18224179
申请日：2023-07-20
发明人： Kalyan Chakravarthy Kavalipurapu , Tomoko Ogura Iwasaki , Erwin E. Yu , Hong-Yan Chen , Yunfei Xu
CPC分类号： G11C16/16 , G06F3/0604 , G06F3/064 , G06F3/0652 , G06F3/0679 , G11C16/0483 , G11C16/08
摘要： A processing device in a memory system connects a first data block of the memory device to a second data block of the memory device to generate a combined data block comprising a first plurality of sub-blocks of the first data block and a second plurality of sub-blocks of the second data block, wherein the connecting includes: for each wordline of a first plurality of wordlines of the first data block, creating a wordline connection short between the respective wordline of the first data block and a corresponding wordline of a second plurality of wordlines of the second data block, wherein the first plurality of wordlines and the second plurality of wordlines comprise data wordlines; and driving a first data wordline of the first data block and a second wordline of the second data block using a single string driver of the memory device.
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公开(公告)号：US11915758B2
公开(公告)日：2024-02-27
申请号：US18095049
申请日：2023-01-10
发明人： Hao T. Nguyen , Tomoko Ogura Iwasaki , Erwin E. Yu , Dheeraj Srinivasan , Sheyang Ning , Lawrence Celso Miranda , Aaron S. Yip , Yoshihiko Kamata
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3459 , G11C11/5621 , G11C11/5671
摘要： Memory devices might include a first storage element, a second storage element, a data line, and a controller. The first storage element is to store a first data bit. The second storage element is to store a second data bit. The data line is selectively connected to the first storage element, the second storage element, and a memory cell. The controller is configured to apply one of four voltage levels to the data line based on the first data bit and the second data bit.
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公开(公告)号：US20230360709A1
公开(公告)日：2023-11-09
申请号：US18224179
申请日：2023-07-20
发明人： Kalyan Chakravarthy Kavalipurapu , Tomoko Ogura Iwasaki , Erwin E. Yu , Hong-Yan Chen , Yunfei Xu
CPC分类号： G11C16/16 , G06F3/0604 , G06F3/0652 , G11C16/0483 , G06F3/0679 , G11C16/08 , G06F3/064
摘要： A processing device in a memory system connects a first data block of the memory device to a second data block of the memory device to generate a combined data block comprising a first plurality of sub-blocks of the first data block and a second plurality of sub-blocks of the second data block, wherein the connecting includes: for each wordline of a first plurality of wordlines of the first data block, creating a wordline connection short between the respective wordline of the first data block and a corresponding wordline of a second plurality of wordlines of the second data block, wherein the first plurality of wordlines and the second plurality of wordlines comprise data wordlines; and driving a first data wordline of the first data block and a second wordline of the second data block using a single string driver of the memory device.
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公开(公告)号：US11749353B2
公开(公告)日：2023-09-05
申请号：US17745852
申请日：2022-05-16
发明人： Kalyan Chakravarthy Kavalipurapu , Tomoko Ogura Iwasaki , Erwin E. Yu , Hong-Yan Chen , Yunfei Xu
CPC分类号： G11C16/16 , G06F3/0604 , G06F3/064 , G06F3/0652 , G06F3/0679 , G11C16/0483 , G11C16/08
摘要： A processing device in a memory system receives an erase request to erase data stored at a data block of a memory device, the erase request identifying a selected sub-block of a plurality of sub-blocks of the data block for erase, each of the plurality of sub-blocks comprising select gate devices (SGDs) and data storage devices. For each sub-block of the plurality of sub-blocks not selected for erase, the processing device applies an input voltage at a bitline of the respective sub-block and applies a plurality of gate voltages to a plurality of wordlines of the respective sub-block, the plurality of wordlines are coupled to the SGDs and to the data storage devices, each voltage of the plurality of voltages applied to a successive wordline of the plurality of wordlines is less than a previous voltage applied to a previous wordline.
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公开(公告)号：US20230170016A1
公开(公告)日：2023-06-01
申请号：US18096072
申请日：2023-01-12
发明人： Dan Xu , Jun Xu , Erwin E. Yu , Paolo Tessariol , Tomoko Ogura Iwasaki
IPC分类号： G11C13/00
CPC分类号： G11C13/003 , G11C13/0038
摘要： Memory array structures might include a first conductive plate connected to memory cells of a first dummy block of memory cells and to memory cells of a second dummy block of memory cells on opposing sides of a first isolation region; a second conductive plate connected to memory cells of the first dummy block of memory cells and to memory cells of the second dummy block of memory cells on opposing sides of a second isolation region; first and second conductors selectively connected to a first global access line, and connected to the first conductive plate on opposing sides of the first isolation region; third and fourth conductors selectively connected to a second global access line, and connected to the second conductive plate on opposing sides of the second isolation region; and a fifth conductor connected to the third conductor and connected to the second conductor.
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公开(公告)号：US20230063656A1
公开(公告)日：2023-03-02
申请号：US17591510
申请日：2022-02-02
发明人： Chulbum Kim , Brian Kwon , Erwin E. Yu , Kitae Park , Taehyun Kim
摘要： A memory device includes a memory array of memory cells and control logic operatively coupled with the memory array. The control logic is to perform operations including: initiating a true erase sub-operation by causing an erase pulse to be applied to one or more sub-blocks of the memory array; tracking, a number of suspend commands received from a processing device during time periods that a memory line of the memory array is caused to ramp towards an erase voltage of the erase pulse; causing, in response to receiving each suspend command, the true erase sub-operation to be suspended to enable performing a non-erase memory operation; and in response to the number of suspend commands satisfying a threshold criterion, alerting the processing device to terminate sending suspend commands until after completion of the true erase sub-operation.
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公开(公告)号：US11562791B1
公开(公告)日：2023-01-24
申请号：US17396825
申请日：2021-08-09
发明人： Hao T. Nguyen , Tomoko Ogura Iwasaki , Erwin E. Yu , Dheeraj Srinivasan , Sheyang Ning , Lawrence Celso Miranda , Aaron S. Yip , Yoshihiko Kamata
摘要： Memory devices might include a first latch to store a first data bit; a second latch to store a second data bit; a data line selectively connected to the first latch, the second latch, and a string of series-connected memory cells; and a controller configured to bias the data line during a programing operation of a selected memory cell. The controller may with the first data bit equal to 0 and the second data bit equal to 0, bias the data line to a first voltage level; with the first data bit equal to 1 and the second data bit equal to 0, bias the data line to a second voltage level; with the first data bit equal to 0 and the second data bit equal to 1, bias the data line to a third voltage level; and with the first data bit equal to 1 and the second data bit equal to 1, bias the data line to a fourth voltage level.
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