公开(公告)号：US20240203508A1

公开(公告)日：2024-06-20

申请号：US18589730

申请日：2024-02-28

Applicant: Micron Technology, Inc.

Inventor： Chulbum Kim ,  Brian Kwon ,  Erwin E. Yu ,  Kitae Park ,  Taehyun Kim

IPC: G11C16/14 ,  G06F3/06 ,  G11C16/04 ,  G11C16/22 ,  G11C16/32

CPC classification number: G11C16/14 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/225 ,  G11C16/32

Abstract: A memory device includes a memory array comprising memory cells and control logic operatively coupled with the memory array. The control logic causes, as part of a true erase sub-operation, an erase pulse to be applied to one or more sub-blocks of the memory array. The control logic tracks a number of suspend commands received from a processing device, including suspend commands received while memory cells of the one or more sub-blocks are being erased. The control logic causes, in response to receiving each suspend command, the true erase sub-operation to be suspended to enable performing a non-erase memory operation. The control logic, in response to the number of suspend commands satisfying a threshold criterion, alerts the processing device to terminate sending suspend commands.

公开(公告)号：US20240170075A1

公开(公告)日：2024-05-23

申请号：US18387217

申请日：2023-11-06

Applicant: Micron Technology, Inc.

Inventor： Kwang Ho Kim ,  Erwin E. Yu

IPC: G11C16/26 ,  G11C16/24

CPC classification number: G11C16/26 ,  G11C16/24

Abstract: Entry of a memory device into a standby mode is determined. During the standby mode of the memory device, a first bias voltage level is caused to be applied to a sense amplifier latch of a sense amplifier of a page buffer circuit of the memory device. During the standby mode, a second bias voltage level is caused to be applied to a set of data latches of the sense amplifier of the page buffer circuit of the memory device, wherein the second bias voltage level is different from the first bias voltage level.

公开(公告)号：US11862257B2

公开(公告)日：2024-01-02

申请号：US17989168

申请日：2022-11-17

Applicant: Micron Technology, Inc.

Inventor： Jun Xu ,  Violante Moschiano ,  Erwin E. Yu

IPC: G11C16/08 ,  G11C16/34 ,  G11C16/26 ,  G11C16/24 ,  G11C16/10

CPC classification number: G11C16/3454 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3404

Abstract: A programming pulse is caused to be applied to a wordline associated with a memory cell of the memory sub-system. A program verify operation is caused to be performed on the memory cell to determine that a measured threshold voltage associated with the memory cell. The measured threshold voltage associated with the memory cell is stored in a sensing node associated with the memory cell. A bitline voltage matching the measured threshold voltage is caused to be applied to a bitline associated with the memory cell to reduce a rate of programming associated with the memory cell.

公开(公告)号：US20230047662A1

公开(公告)日：2023-02-16

申请号：US17445045

申请日：2021-08-13

Applicant: Micron Technology, Inc.

Inventor： Erwin E. Yu ,  Michele Piccardi ,  Surendranath C. Eruvuru

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  G11C5/02 ,  H01L23/538 ,  H01L27/092

Abstract: A microelectronic device comprises a base structure, a memory array overlying the base structure, and a conductive pad tier overlying the memory array. The base structure comprises a logic region including logic devices. The memory array comprises vertically extending strings of memory cells within a horizontal area of the logic region of the base structure. The conductive pad tier comprises first conductive pads substantially outside of the horizontal area of the logic region of the base structure, and second conductive pads horizontally neighboring the first conductive pads and within the horizontal area of the logic region of the base structure. Memory devices and electronic systems are also described.

公开(公告)号：US20220404408A1

公开(公告)日：2022-12-22

申请号：US17894227

申请日：2022-08-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dan Xu ,  Jun Xu ,  Erwin E. Yu

IPC: G01R27/26 ,  G11C16/08 ,  G11C16/04 ,  G01R27/08

Abstract: Apparatus having an array of memory cells and a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to apply a reference current to a selected access line, determine a time difference between a voltage level of a near end of the selected access line being deemed to exceed a first voltage level while applying the reference current and the voltage level of the near end of the selected access line being deemed to exceed a second voltage level while applying the reference current, and determine a capacitance value of the selected access line in response to a current level of the reference current, the time difference, and a voltage difference between the second voltage level and the first voltage level.

公开(公告)号：US20180366203A1

公开(公告)日：2018-12-20

申请号：US16111319

申请日：2018-08-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luyen Vu ,  Kalyan C. Kavalipurau ,  Jae-Kwan Park ,  Erwin E. Yu

IPC: G11C16/26 ,  G11C16/32 ,  G11C16/30 ,  G11C16/24 ,  G11C16/04 ,  G11C7/04 ,  G11C5/14

CPC classification number: G11C16/26 ,  G11C5/145 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/30 ,  G11C16/32

Abstract: Apparatus and methods to vary, in response to temperature, a precharge voltage level of a sense node during a sense operation, a sense node develop time during the sense operation, and/or a ratio of a deboost voltage level capacitively decoupled from the sense node to a boost voltage level capacitively coupled to the sense node during the sense operation.

公开(公告)号：US10127988B2

公开(公告)日：2018-11-13

申请号：US15248692

申请日：2016-08-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luyen Vu ,  Kalyan C. Kavalipurau ,  Jae-Kwan Park ,  Erwin E. Yu

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  G11C7/04 ,  G11C16/30 ,  G11C16/32 ,  G11C5/14

Abstract: Sense circuits and methods to vary, in response to temperature, a precharge voltage level of a sense node during a sense operation, a sense node develop time during the sense operation, and/or a ratio of a deboost voltage level capacitively decoupled from the sense node to a boost voltage level capacitively coupled to the sense node during the sense operation.

公开(公告)号：US20180061497A1

公开(公告)日：2018-03-01

申请号：US15248692

申请日：2016-08-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luyen Vu ,  Kalyan C. Kavalipurau ,  Jae-Kwan Park ,  Erwin E. Yu

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  G11C7/04 ,  G11C16/30

CPC classification number: G11C16/26 ,  G11C5/145 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/30 ,  G11C16/32

Abstract: Sense circuits and methods to vary, in response to temperature, a precharge voltage level of a sense node during a sense operation, a sense node develop time during the sense operation, and/or a ratio of a deboost voltage level capacitively decoupled from the sense node to a boost voltage level capacitively coupled to the sense node during the sense operation.

公开(公告)号：US12068037B2

公开(公告)日：2024-08-20

申请号：US18224179

申请日：2023-07-20

Applicant: Micron Technology, Inc.

Inventor： Kalyan Chakravarthy Kavalipurapu ,  Tomoko Ogura Iwasaki ,  Erwin E. Yu ,  Hong-Yan Chen ,  Yunfei Xu

IPC: G11C16/16 ,  G06F3/06 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/16 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/08

Abstract: A processing device in a memory system connects a first data block of the memory device to a second data block of the memory device to generate a combined data block comprising a first plurality of sub-blocks of the first data block and a second plurality of sub-blocks of the second data block, wherein the connecting includes: for each wordline of a first plurality of wordlines of the first data block, creating a wordline connection short between the respective wordline of the first data block and a corresponding wordline of a second plurality of wordlines of the second data block, wherein the first plurality of wordlines and the second plurality of wordlines comprise data wordlines; and driving a first data wordline of the first data block and a second wordline of the second data block using a single string driver of the memory device.

公开(公告)号：US11915758B2

公开(公告)日：2024-02-27

申请号：US18095049

申请日：2023-01-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hao T. Nguyen ,  Tomoko Ogura Iwasaki ,  Erwin E. Yu ,  Dheeraj Srinivasan ,  Sheyang Ning ,  Lawrence Celso Miranda ,  Aaron S. Yip ,  Yoshihiko Kamata

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C11/56

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3459 ,  G11C11/5621 ,  G11C11/5671

Abstract: Memory devices might include a first storage element, a second storage element, a data line, and a controller. The first storage element is to store a first data bit. The second storage element is to store a second data bit. The data line is selectively connected to the first storage element, the second storage element, and a memory cell. The controller is configured to apply one of four voltage levels to the data line based on the first data bit and the second data bit.