公开(公告)号：US09978438B2

公开(公告)日：2018-05-22

申请号：US15614037

申请日：2017-06-05

Applicant: Micron Technology, Inc.

Inventor： Hiroki Fujisawa

IPC: G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4093 ,  G11C11/4091

CPC classification number: G11C11/4076 ,  G11C7/1048 ,  G11C7/1069 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096

Abstract: A device includes a first data terminal, a second data terminal, a first switching buffer coupled between a data node and the first data terminal and a second switching buffer coupled between the data node and the second data terminal. The first switching buffer and the second switching buffer are arranged such that a distance between the first switching buffer and the second data terminal is shorter than a distance between the second switching buffer and the second data terminal and that a distance between the first switching buffer and the first data terminal is shorter than a distance between the second switching buffer and the first data terminal.

公开(公告)号：US20180061475A1

公开(公告)日：2018-03-01

申请号：US15614037

申请日：2017-06-05

Applicant: Micron Technology, Inc.

Inventor： Hiroki Fujisawa

IPC: G11C11/4076 ,  G11C11/4096 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4093

CPC classification number: G11C11/4076 ,  G11C7/1048 ,  G11C7/1069 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096

Abstract: A device includes a first data terminal, a second data terminal, a first switching buffer coupled between a data node and the first data terminal and a second switching buffer coupled between the data node and the second data terminal. The first switching buffer and the second switching buffer are arranged such that a distance between the first switching buffer and the second data terminal is shorter than a distance between the second switching buffer and the second data terminal and that a distance between the first switching buffer and the first data terminal is shorter than a distance between the second switching buffer and the first data terminal.

公开(公告)号：US09881665B2

公开(公告)日：2018-01-30

申请号：US15460206

申请日：2017-03-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hiromasa Takeda ,  Hiroki Fujisawa

IPC: G11C7/10 ,  G11C11/4093 ,  G11C11/4074 ,  G11C11/4094

CPC classification number: G11C11/4093 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1057 ,  G11C11/4074 ,  G11C11/4094 ,  G11C29/022 ,  G11C29/028 ,  G11C2207/2254

Abstract: An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power source potential, a third terminal configured to receive a second power source potential lower than the first power source potential, a fourth terminal configured to be coupled to a calibration resistor, an output buffer including first to third nodes coupled to the first to third terminals respectively, and a replica circuit including fourth and fifth nodes coupled to the second and third terminals respectively, and sixth node coupled to the fourth terminal.

公开(公告)号：US20170309320A1

公开(公告)日：2017-10-26

申请号：US15139102

申请日：2016-04-26

Applicant: Micron Technology, Inc.

Inventor： Shuichi Ishibashi ,  Kazutaka Miyano ,  Hiroki Fujisawa

IPC: G11C8/18 ,  G11C7/10 ,  G11C8/10 ,  G11C7/22

CPC classification number: G11C8/18 ,  G11C7/1015 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/10 ,  G11C11/4076 ,  G11C29/023 ,  G11C29/024 ,  G11C29/028 ,  G11C2207/2254 ,  G11C2207/2272

Abstract: Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that provides a reference clock signal and a system clock signal based on an external clock signal; a command decoder that latches command signals with the system clock signal and further provides a signal based on the command signals; and a command delay adjustment circuit including: a clock synchronizing circuit that receives the signal, latches the signal with the system clock signal and provides a clock-synchronized read signal responsive to a shift cycle parameter.

公开(公告)号：US09786352B2

公开(公告)日：2017-10-10

申请号：US14447287

申请日：2014-07-30

Applicant: Micron Technology, Inc.

Inventor： Kenji Yoshida ,  Hiroki Fujisawa

IPC: G11C11/406 ,  G11C11/4074 ,  G11C11/4076

CPC classification number: G11C11/40626 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4094 ,  G11C2211/4061

Abstract: Disclosed herein is a semiconductor device that includes: a memory cell array including a plurality of memory groups each having a plurality of memory cells, the memory groups being selected by mutually different addresses; a first control circuit periodically executing a refresh operation on the memory groups in response to a first refresh command; and a second control circuit setting a cycle of executing the refresh operation by the first control circuit. The second control circuit sets the cycle to a first cycle until executing the refresh operation to all the memory groups after receiving the first refresh command, and the second control circuit sets the cycle to a second cycle that is longer than the first cycle after executing the refresh operation to all the memory groups.

公开(公告)号：US09530459B2

公开(公告)日：2016-12-27

申请号：US14523704

申请日：2014-10-24

Applicant: Micron Technology, Inc.

Inventor： Shingo Mitsubori ,  Hiroki Fujisawa

IPC: G11C7/00 ,  G11C5/02 ,  G11C7/08 ,  G11C7/10 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

CPC classification number: G11C5/025 ,  G11C7/08 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

Abstract: A semiconductor memory disclosed in this disclosure includes first and second memory cell arrays, a first main data line that transfers the read data read from the first memory cell array, a second main data line that transfers the read data read from the second memory cell array, a main amplifier coupled to the second main data line, and a repeater circuit coupled to the first main data line and the second main data line.

Abstract translation: 本公开中公开的半导体存储器包括第一和第二存储器单元阵列，传送从第一存储单元阵列读取的读取数据的第一主数据线，传送从第二存储单元阵列读取的读取数据的第二主数据线 耦合到第二主数据线的主放大器，以及耦合到第一主数据线和第二主数据线的中继器电路。

公开(公告)号：US09473146B2

公开(公告)日：2016-10-18

申请号：US14613192

申请日：2015-02-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hiroki Fujisawa

IPC: H03B19/00 ,  H03K23/40 ,  H03K21/02

CPC classification number: H03K23/40 ,  H03K21/026

Abstract: Apparatuses and methods for low power counting circuits are described herein. An example apparatus may include a frequency divider configured to receive an input clock signal and adjust a frequency of the clock signal to provide an intermediate clock signal. The apparatus may further include a counter coupled to the frequency divider and configured to receive the intermediate clock signal. The counter may further be configured to provide a plurality of timing signals based on the intermediate clock signal. The apparatus may further include a frequency multiplier including a plurality of logic gates. Each of the plurality of logic gates may be coupled to the counter and configured to receive a respective first timing signal of the plurality of timing signals and at least one of the intermediate clock signal or a respective second timing signal of the plurality of timing signals.

Abstract translation: 本文描述了用于低功率计数电路的装置和方法。 示例性装置可以包括分频器，其被配置为接收输入时钟信号并且调整时钟信号的频率以提供中间时钟信号。 该装置还可以包括耦合到分频器并被配置为接收中间时钟信号的计数器。 计数器还可以被配置为基于中间时钟信号提供多个定时信号。 该装置还可以包括包括多个逻辑门的倍频器。 多个逻辑门中的每一个可以耦合到计数器并且被配置为接收多个定时信号的相应第一定时信号以及多个定时信号中的中间时钟信号或相应的第二定时信号中的至少一个。

公开(公告)号：US09336856B2

公开(公告)日：2016-05-10

申请号：US14638836

申请日：2015-03-04

Applicant: Micron Technology, Inc.

Inventor： Hiroto Kinoshita ,  Hiroki Fujisawa

IPC: G11C8/00 ,  G11C11/408 ,  G11C11/4093 ,  G11C7/10

CPC classification number: G11C11/4082 ,  G11C7/10 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/4093 ,  G11C2207/105

Abstract: A device includes a plurality of input terminals, a control circuit, and a plurality of signal buses. Each of the signal buses is coupled between the control circuit and an associated one of the plurality of input terminals and includes one or more first buffers, one or more second buffers and at least one latch circuit coupled between the one or more first buffers and the one or more second buffers. The one or more first buffers of one of the signal buses are different in number from the one or more first buffers of a different one of the signal buses.

Abstract translation: 一种装置包括多个输入端子，一个控制电路和多个信号总线。 信号总线中的每一个耦合在控制电路和多个输入终端中相关联的一个之间，并且包括一个或多个第一缓冲器，一个或多个第二缓冲器和耦合在一个或多个第一缓冲器和 一个或多个第二缓冲器。 一个信号总线的一个或多个第一缓冲器的数量与不同信号总线的一个或多个第一缓冲器不同。

公开(公告)号：US11227861B2

公开(公告)日：2022-01-18

申请号：US17125651

申请日：2020-12-17

Applicant: Micron Technology, Inc.

Inventor： Hiroki Fujisawa ,  Charles L. Ingalls ,  Richard J. Hill ,  Gurtej S. Sandhu ,  Scott J. Derner

IPC: G11C11/40 ,  H01L25/18 ,  G11C11/4091 ,  H01L23/528 ,  H01L27/108 ,  G11C11/408 ,  H01L29/78

Abstract: Some embodiments include an integrated assembly having a base comprising sense-amplifier-circuitry, a first deck over the base, and a second deck over the first deck. The first deck includes a first portion of a first array of first memory cells, and includes a first portion of a second array of second memory cells. The second deck includes a second portion of the first array of the first memory cells, and includes a second portion of the second array of the second memory cells. A first digit line is associated with the first array, and a second digit line is associated with the second array. The first and second digit lines are comparatively coupled with one another through the sense-amplifier-circuitry.

公开(公告)号：US11081468B2

公开(公告)日：2021-08-03

申请号：US16553549

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： Hiroki Fujisawa ,  Raj K. Bansal ,  Shunji Kuwahara ,  Mitsuaki Katagiri ,  Satoshi Isa

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  G11C11/4096

Abstract: Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.