Abstract:
A memory device includes a memory controller and a non-volatile memory communicatively coupled to the memory controller and storing a mapping table and a journal table. The memory controller is configured to write data and a logical address of the data into the non-volatile memory, load mapping information related to the logical address of the data from the mapping table of the non-volatile memory into a mapping cache of the memory controller, update the mapping cache with an updated mapping relationship between the logical address of the data and a physical address of the data, and perform a journaling operation to write the updated mapping relationship into the journal table.
Abstract:
An erasing method and a memory device are provided. The memory device includes a plurality of memory blocks. Each of the memory blocks has n sub-blocks. The erasing method includes the following steps. A first erase region is selected from a first memory block of the memory blocks, and the first erase region includes at least one sub-block. A sub-block erase operation is performed on the first erase region of the first memory block.
Abstract:
A memory system includes a memory array including a plurality of memory cells, and an encoder operatively coupled to the memory array, for encoding an original data element to be programmed into the memory cells into a uniform data element in which the number of “0”s approximately equals the number of “1”s.
Abstract:
A method and a device for performing a polar codes channel-aware procedure are provided. A plurality of bit-channels have a polar code construction which is dynamic. The method includes the following steps. A plurality of reliability indices of some of the bit-channels are ranked. Whether an updating condition is satisfied is determined according to a ranking sequence of the reliability indices. If the updating condition is satisfied, the polar code construction is updated according to the ranking sequence of the reliability indices.
Abstract:
A first memory cell including a phase change material. The first memory cell is programmable to store one data value of a plurality of data values. The plurality of data values are represented by a plurality of non-overlapping ranges of resistance of the first memory cell. At least one testing pulse is applied to the first memory cell to establish a cell resistance of the first memory cell in an intermediate range of resistance, the intermediate range of resistance in between first and second adjacent ranges in the plurality of non-overlapping ranges of resistance representing the plurality of data values. After applying the at least one testing pulse to the first memory cell, it is determined whether to apply at least one healing pulse to repair the first memory cell, depending on relative values of (i) the cell resistance in the intermediate range of resistance and (ii) a reference resistance in the intermediate range of resistance.
Abstract:
A method is provided for managing a file system including data objects. The data objects, indirect pointers and source pointers are stored in containers that have addresses and include addressable units of a memory. The objects are mapped to addresses for corresponding containers. The indirect pointer in a particular container points to the address of a container in which the corresponding object is stored. The source pointer in the particular container points to the address of the container to which the object in the particular container is mapped. An object in a first container is moved to a second container. The source pointer in the first container is used to find a third container to which the object is mapped. The indirect pointer in the third container is updated to point to the second container. The source pointer in the second container is updated to point to the third container.
Abstract:
A method is provided for managing a memory device including a plurality of physical memory segments. A logical memory space is classified into a plurality of classifications based on usage specifications. The plurality of physical memory segments is allocated to corresponding logical addresses based on the plurality of classifications, and on usage statistics of the physical memory segments. A data structure is maintained recording translation between logical addresses in the logical memory space and physical addresses of the physical memory segments. The plurality of classifications includes a first classification and a second classification having different usage statistic requirements than the first classification. Logical addresses having the second classification can be redirected to physical segments allocated to logical addresses having the first classification, and the data structure can be updated to record redirected logical addresses. A free command can release a physical memory segment allocated for main memory use.
Abstract:
A memory sensing method is provided. The memory sensing method comprises the following steps: sensing a first memory unit to obtain a first sensing result; sensing a second memory unit to obtain a second sensing result; and looking up a one-time sensing table according to the first and second sensing results to obtain an output data.
Abstract:
An operating method for a memory, the memory comprising at least one memory block including a plurality of first pages and a plurality of second pages corresponding to the first pages, the operating method including the following steps: determining whether a target first page of the first pages is valid, wherein the target first page is corresponding to a target second page of the second pages; if the target first page is valid, performing first type programming on the target second page; if the target first page is invalid, performing second type programming on the target second page.
Abstract:
Multiple measurements are made with one memory sense operation having a first word line sensing voltage on a memory cell. The multiple measurements include a first measurement, of whether the memory cell stores either: (a) data corresponding to a first set of one or more threshold voltage ranges below the first word line sensing voltage of the one memory sense operation, or (b) data corresponding to a second set of one or more threshold voltage ranges above the first word line sensing voltage of the one memory sense operation. The multiple measurements include a second measurement, of error correction data of the memory cell indicating relative position within a particular threshold voltage range of a stored threshold voltage in the memory cell.