专利检索 ap:("Masami Goi" OR "Kazuya Kameo" OR "Jiro Sawada" OR "Kazunori Hanada" OR "Masaharu Tamai" OR "Kiyoshi Oguma") AND inv:"Jiro Sawada" 第 2 页

11.

发明授权
2-(p-Prenylphenyl)propionic acid 失效
标题翻译： 2-（对 - 戊基苯基）丙酸

公开(公告)号：US4251543A

公开(公告)日：1981-02-17

申请号：US45090

申请日：1979-06-04

申请人： Takehiro Amano , Jiro Sawada , Michitada Sasajima

发明人： Takehiro Amano , Jiro Sawada , Michitada Sasajima

IPC分类号： A61K31/19 , A61P25/04 , A61P29/00 , C07C51/00 , C07C57/42 , C07C67/00 , C07C253/00 , C07C255/33 , C07C69/618

CPC分类号： C07C57/42

摘要： 2-(p-prenylphenyl)propionic acid and pharmaceutically acceptable salts thereof are disclosed. They exhibit anti-inflammatory and analgesic activity with low gastrointestinal action.

摘要翻译： 公开了2-（对异戊基苯基）丙酸及其药学上可接受的盐。它们具有抗消炎和镇痛作用，具有低胃肠作用。

12.

发明授权
Semiconductor memory device and defect remedying method thereof 失效

公开(公告)号：US07345929B2

公开(公告)日：2008-03-18

申请号：US11714867

申请日：2007-03-07

申请人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata

发明人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata

IPC分类号： G11C7/10

CPC分类号： H01L24/06 , G11C5/025 , G11C5/04 , G11C5/063 , G11C11/406 , G11C29/06 , G11C29/12005 , G11C29/12015 , G11C29/24 , G11C29/34 , G11C29/50 , G11C29/50012 , G11C29/70 , G11C29/80 , G11C29/804 , G11C29/832 , G11C29/844 , G11C2029/2602 , H01L24/05 , H01L24/45 , H01L24/48 , H01L27/0207 , H01L27/105 , H01L27/10897 , H01L27/11898 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/05624 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48624 , H01L2224/73215 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01021 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01037 , H01L2924/01038 , H01L2924/01039 , H01L2924/01041 , H01L2924/01043 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01054 , H01L2924/01055 , H01L2924/01058 , H01L2924/01059 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01083 , H01L2924/01084 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012

摘要： A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.

13.

发明授权
Semiconductor memory device and defect remedying method thereof 失效
标题翻译：半导体存储器件及其缺陷补救方法

公开(公告)号：US07016236B2

公开(公告)日：2006-03-21

申请号：US11101504

申请日：2005-04-08

申请人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata

发明人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata

IPC分类号： G11C16/04

CPC分类号： H01L24/06 , G11C5/025 , G11C5/04 , G11C5/063 , G11C11/406 , G11C29/06 , G11C29/12005 , G11C29/12015 , G11C29/24 , G11C29/34 , G11C29/50 , G11C29/50012 , G11C29/70 , G11C29/80 , G11C29/804 , G11C29/832 , G11C29/844 , G11C2029/2602 , H01L24/05 , H01L24/45 , H01L24/48 , H01L27/0207 , H01L27/105 , H01L27/10897 , H01L27/11898 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/05624 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48624 , H01L2224/73215 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01021 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01037 , H01L2924/01038 , H01L2924/01039 , H01L2924/01041 , H01L2924/01043 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01054 , H01L2924/01055 , H01L2924/01058 , H01L2924/01059 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01083 , H01L2924/01084 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012

摘要： A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.

摘要翻译： 形成在半导体芯片上的半导体存储器件包括多个第一存储器阵列，多个第二存储器阵列，第一电压发生器和多个第一焊盘。半导体芯片被分成第一矩形区域，第二矩形区域和第三矩形区域，并且第三矩形区域被布置在第一矩形区域和第二矩形区域之间。多个第一存储器阵列形成在第一矩形区域中。多个第二存储器阵列形成在第二矩形区域中。电压发生器和多个第一接合焊盘被布置在第三矩形区域中。多个第一接合焊盘布置在第一矩形区域和电压发生器之间，并且在电压发生器和多个第二存储器阵列之间没有布置接合焊盘。

14.

发明授权
Semiconductor memory device and defect remedying method thereof 有权

公开(公告)号：US6049500A

公开(公告)日：2000-04-11

申请号：US153462

申请日：1998-09-15

申请人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata

发明人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata

IPC分类号： G11C5/00 , G11C5/02 , G11C5/06 , G11C11/34 , G11C11/406 , H01L23/485 , G11C8/00

CPC分类号： G11C5/025 , G11C11/406 , G11C5/063 , H01L24/05 , H01L24/06 , H01L24/48 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48599 , H01L2224/73215 , H01L24/45 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/0101 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01021 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01033 , H01L2924/01037 , H01L2924/01038 , H01L2924/01039 , H01L2924/01041 , H01L2924/01043 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01054 , H01L2924/01055 , H01L2924/01058 , H01L2924/01059 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/01087 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025

摘要： Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

15.

发明授权
Semiconductor integrated circuit device, and process and apparatus for manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法和装置

公开(公告)号：US5910010A

公开(公告)日：1999-06-08

申请号：US732215

申请日：1997-02-18

申请人： Hirotaka Nishizawa , Tomoyoshi Miura , Ichirou Anjou , Masamichi Ishihara , Masahiro Yamamura , Sadao Morita , Takashi Araki , Kiyoshi Inoue , Toshio Sugano , Tetsuji Kohara , Toshio Yamada , Yasushi Sekine , Yoshiaki Anata , Masakatsu Goto , Norihiko Kasai , Shinobu Takeura , Mutsuo Tsukuda , Yasunori Yamaguchi , Jiro Sawada , Hidetoshi Iwai , Seiichiro Tsukui , Tadao Kaji , Noboru Shiozawa

发明人： Hirotaka Nishizawa , Tomoyoshi Miura , Ichirou Anjou , Masamichi Ishihara , Masahiro Yamamura , Sadao Morita , Takashi Araki , Kiyoshi Inoue , Toshio Sugano , Tetsuji Kohara , Toshio Yamada , Yasushi Sekine , Yoshiaki Anata , Masakatsu Goto , Norihiko Kasai , Shinobu Takeura , Mutsuo Tsukuda , Yasunori Yamaguchi , Jiro Sawada , Hidetoshi Iwai , Seiichiro Tsukui , Tadao Kaji , Noboru Shiozawa

IPC分类号： H01L21/56 , H01L21/98 , H01L23/495 , H01L25/065 , H01L21/52 , H01L21/58 , H01L21/60

CPC分类号： H01L24/06 , H01L21/565 , H01L23/4951 , H01L23/49575 , H01L25/0657 , H01L25/50 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/32245 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/4826 , H01L2224/49171 , H01L2224/73215 , H01L2225/06527 , H01L2225/06551 , H01L2225/06582 , H01L2225/06586 , H01L2225/06589 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/0105 , H01L2924/01055 , H01L2924/01058 , H01L2924/01075 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/3011 , H01L2924/3025 , H01L2924/351

摘要： A method of manufacturing a semiconductor integrated circuit device includes the steps of constructing a plurality of lead frames having leads which each include an inner portion and an outer portion and electrically connecting a semiconductor chip to the inner portions of the leads of each frame. The lead frames are then stacked one above each other to form a vertical stack and plates are then inserted between each of the lead frames with each plate having an opening in the center whereby a central cavity is formed in the stack. The stack is then placed between a top mold member and a bottom mold member and a resin is injected into the central cavity whereupon the resin is cured to form a single resin package encapsulating the semiconductor chips. The resin package is then released from the mold members.

摘要翻译： PCT No.PCT / JP95 / 00662 Sec。 371日期1997年2月18日 102（e）日期1997年2月18日PCT提交1995年4月5日PCT公布。 WO95 / 29506 PCT公开号日期：1995年11月2日制造半导体集成电路器件的方法包括以下步骤：构造多个引线框架，引线框架各自包括内部部分和外部部分，并将半导体芯片电连接到引线的内部每一帧。然后将引线框架彼此堆叠以形成垂直堆叠，然后将板在每个引线框架之间插入，每个板在中心具有开口，由此在堆叠中形成中心空腔。然后将堆叠放置在顶模构件和底模构件之间，并将树脂注入到中心腔中，由此树脂固化以形成封装半导体芯片的单个树脂封装。然后将树脂包装从模具部件中释放出来。

16.

发明授权
Semiconductor memory including an arrangement to permit external monitoring of an internal control signal 失效
标题翻译：半导体存储器包括允许外部监视内部控制信号的装置

公开(公告)号：US5151881A

公开(公告)日：1992-09-29

申请号：US485406

申请日：1988-04-25

申请人： Kazuhiko Kajigaya , Jiro Sawada

发明人： Kazuhiko Kajigaya , Jiro Sawada

IPC分类号： G11C11/401 , G11C7/22 , G11C29/00 , G11C29/14 , G11C29/48

CPC分类号： G11C7/22 , G11C29/14 , G11C29/48

摘要： A semiconductor memory comprises a memory array including a plurality of memory cells, a peripheral circuit which executes either an information write or read operation with respect to one or more memory cells selected from the plurality of memory cells, a timing control circuit which forms at least one internal control signal for controlling the peripheral circuit, and at least one external terminal for delivering said at least one internal control signal to the outside of the semiconductor memory. For example, the peripheral circuit can include an arrangement to permit the peripheral circuit to operate in a test mode to deliver the internal control signal to the external terminal to allow external testing of the operation of the internal control signal.

摘要翻译： 一种半导体存储器包括一个包括多个存储单元的存储器阵列，一个对从多个存储器单元中选出的一个或多个存储单元执行信息写入或读取操作的外围电路，至少形成一个定时控制电路用于控制外围电路的一个内部控制信号，以及用于将所述至少一个内部控制信号传送到半导体存储器的外部的至少一个外部端子。例如，外围电路可以包括允许外围电路在测试模式下操作以将内部控制信号传送到外部端子的装置，以允许内部控制信号的操作的外部测试。

17.

发明授权
Antibiotic TM-481 derived from microorganism of the streptomyces ribosidificus group 失效
标题翻译：抗生素TM-481衍生自{i streptomyces ribosidificus {l group

公开(公告)号：US3950514A

公开(公告)日：1976-04-13

申请号：US503165

申请日：1974-09-04

申请人： Jiro Sawada , Sadafumi Omura , Michinori Shibata , Sadao Machida

发明人： Jiro Sawada , Sadafumi Omura , Michinori Shibata , Sadao Machida

IPC分类号： A61K35/74 , C07G11/00 , C12P1/06 , A61K35/00

CPC分类号： A61K36/06 , C07G11/00 , Y10S435/886

摘要： A new polyether group antibiotic, TM-481, having the estimated empirical formula C.sub.42-45 H.sub.71-75 O.sub.14-15 Na and possessing an antibacterial activity against pathogenic microorganisms, particularly Gram-positive bacteria is obtained by culturing a TM-481 producing microorganism of the Streptomyces ribosidificus group in a nutrient medium therefor.

摘要翻译： 通过培养产生TM-481的链霉菌的微生物获得具有估计经验式C42-45H71-75O14-15Na并且具有抗病原微生物，特别是革兰氏阳性菌的抗菌活性的新型聚醚组抗生素TM-481 核糖体组在营养培养基中。