公开(公告)号：US20060083046A1

公开(公告)日：2006-04-20

申请号：US11245075

申请日：2005-10-07

申请人： Masashi Agata ,  Masanori Shirahama ,  Toshiaki Kawasaki ,  Ryuji Nishihara

发明人： Masashi Agata ,  Masanori Shirahama ,  Toshiaki Kawasaki ,  Ryuji Nishihara

IPC分类号： G11C17/00

CPC分类号： G11C17/18

摘要： A fuse device and a program transistor are connected in series with each other. A flip-flop turns ON, in response to a start signal, the program transistor to start program of the fuse device. A 2-input NAND circuit outputs an end signal at a time point where change in a resistance value of the fuse device is increased to reach a predetermined level while monitoring change in the resistance value of the fuse device through change in a voltage at a junction point of the fuse device and the program transistor. The flip-flop turns OFF, in response to the end signal, the program transistor to automatically terminate the program of the fuse device. Thus, the resistance value of the fuse device is increased to the predetermined level in a minimum program time.

摘要翻译： 熔丝器件和程序晶体管彼此串联连接。 触发器响应于启动信号而导通，程序晶体管开始保险丝装置的编程。 2输入NAND电路在熔断器件的电阻值的变化增加以达到预定值的时间点输出结束信号，同时通过接点处的电压变化来监测熔丝器件的电阻值的变化 保险丝装置和程序晶体管的点。 触发器关闭，响应于结束信号，程序晶体管自动终止保险丝装置的程序。 因此，保险丝装置的电阻值在最小程序时间内增加到预定电平。

公开(公告)号：US07031199B2

公开(公告)日：2006-04-18

申请号：US10815709

申请日：2004-04-02

申请人： Naoki Kuroda ,  Masashi Agata

发明人： Naoki Kuroda ,  Masashi Agata

IPC分类号： G11C11/34

CPC分类号： G11C7/22 ,  G11C7/1072 ,  G11C2207/2281

摘要： A port A of the path including a first transistor of a memory cell to be accessed, a first bit line pair, a first column selection switch and a data line pair interleaves with a port B of the path including a second transistor of the memory cell to be accessed, a second bit line pair, a second column selection switch and the data line pair in two cycles of a clock. A read amplifier amplifies data transferred from a bit line pair to the data line pair and outputs the resultant data to an input/output buffer in one cycle of the clock. The input/output buffer outputs the data received from the read amplifier to the outside in one cycle of the clock.

公开(公告)号：US07002865B2

公开(公告)日：2006-02-21

申请号：US10935278

申请日：2004-09-08

申请人： Masashi Agata ,  Masanori Shirahama ,  Toshiaki Kawasaki ,  Ryuji Nishihara

发明人： Masashi Agata ,  Masanori Shirahama ,  Toshiaki Kawasaki ,  Ryuji Nishihara

IPC分类号： G11C7/02

CPC分类号： G11C16/0425

摘要： A nonvolatile semiconductor memory device includes: a first bit cell including a first MOS transistor whose source and drain are connected to form a first control gate and a second MOS transistor which has a floating gate in common with the first MOS transistor; a second bit cell including a third MOS transistor whose source and drain are connected to form a second control gate and a fourth MOS transistor which has a floating gate in common with the third MOS transistor; and a differential amplifier which receives input signals from drains of the respective second and fourth MOS transistors.

摘要翻译： 非易失性半导体存储器件包括：第一位单元，包括其源极和漏极连接以形成第一控制栅极的第一MOS晶体管和具有与第一MOS晶体管共同的浮动栅极的第二MOS晶体管; 第二位单元，包括其源极和漏极连接以形成第二控制栅极的第三MOS晶体管和具有与第三MOS晶体管共同的浮置栅极的第四MOS晶体管; 以及差分放大器，其从相应的第二和第四MOS晶体管的漏极接收输入信号。

公开(公告)号：US06914840B2

公开(公告)日：2005-07-05

申请号：US10790135

申请日：2004-03-02

申请人： Masashi Agata

发明人： Masashi Agata

IPC分类号： H01L27/108 ,  G11C7/12 ,  G11C7/14 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4094 ,  G11C11/4099 ,  H01L21/8242 ,  G11C7/02

CPC分类号： H01L27/10897 ,  G11C7/12 ,  G11C7/14 ,  G11C11/4094 ,  G11C11/4099

摘要： Data reading speed of a DRAM is enhanced without causing an increase in the power consumption and in the chip area. To that end, when data is read, a pair of bit lines is precharged to a GND level, while a dummy cell is charged at a power supply voltage. Immediately after a word line and a dummy word line are activated and their respective potentials are increased by the threshold voltage of an access transistor, a main capacitor and a dummy capacitor are electrically connected to the bit lines, thereby allowing the data to fade in. The resultant potential difference between the pair of bit lines is detected and amplified by a sense amplifier, thereby enabling the data to be read. The capacitance of the dummy capacitor is about half of that of the main capacitor, so that the dummy capacitor can be precharged at the power supply voltage.

摘要翻译： 增强DRAM的数据读取速度，而不会增加功耗和芯片区域。 为此，当读取数据时，一对位线被预充电到GND电平，而虚设单元以电源电压被充电。 在字线和虚拟字线被激活并且它们各自的电位被存取晶体管的阈值电压增加之后，主电容器和虚拟电容器电连接到位线，从而允许数据淡入。 一对位线之间的合成电位差由读出放大器检测和放大，从而使数据能被读取。 虚拟电容器的电容大约是主电容器的电容的一半，这样虚拟电容器可以在电源电压下进行预充电。

公开(公告)号：US5629903A

公开(公告)日：1997-05-13

申请号：US632826

申请日：1996-04-16

申请人： Masashi Agata

发明人： Masashi Agata

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C8/10 ,  G11C11/408 ,  H01L27/10 ,  G11C8/00

CPC分类号： G11C7/1072 ,  G11C8/10

摘要： This invention discloses a synchronous DRAM. An address counter provides a column address of eight bits. The low-order four bits of the column address are assigned to a first column predecoder while the high-order four bits are assigned to a second column predecoder. The first column predecoder provides first predecode signals which are activated in synchronization with a clock leading edge of an internal clock signal and deactivated in synchronization with a clock trailing edge subsequent to the clock leading edge. The second column predecoder provides second predecode signals which make a transition in synchronization with the clock trailing edge. A column decoder sequentially activates column-select lines of a memory cell array according to the AND obtained from all combinations of the first predecode signals and the second predecode signals. Fast, low power column-select line activation is accomplished accordingly.

摘要翻译： 本发明公开了一种同步DRAM。 地址计数器提供8位的列地址。 列地址的低位四位被分配给第一列预解码器，而高位四位被分配给第二列预解码器。 第一列预解码器提供与内部时钟信号的时钟前沿同步地激活的第一预解码信号，并且与时钟前沿之后的时钟后沿同步地去激活。 第二列预解码器提供与时钟后沿同步的第二预解码信号。 列解码器根据从第一预解码信号和第二预解码信号的所有组合获得的AND顺序激活存储器单元阵列的列选择行。 快速，低功率的列选择线激活相应地完成。

公开(公告)号：US20050162954A1

公开(公告)日：2005-07-28

申请号：US11038025

申请日：2005-01-21

申请人： Ryuji Nishihara ,  Masashi Agata ,  Toshiaki Kawasaki ,  Masanori Shirahama

发明人： Ryuji Nishihara ,  Masashi Agata ,  Toshiaki Kawasaki ,  Masanori Shirahama

IPC分类号： G11C7/02 ,  G11C11/409 ,  G11C11/419 ,  G11C29/00 ,  G11C29/50 ,  H01L27/105

CPC分类号： G11C29/50 ,  G11C2029/1204 ,  G11C2029/5004

摘要： In a normal operation, an output of a differential amplifier for amplifying a difference between first and second bit cells is output as readout data. In a test mode, when a first control signal is set to be “H”, the output of the differential amplifier is fixed to be “H” and thus an output of the first bit cell is read out through gates.

摘要翻译： 在正常操作中，输出用于放大第一和第二位单元之间的差分的差分放大器的输出作为读出数据。 在测试模式中，当第一控制信号被设置为“H”时，差分放大器的输出被固定为“H”，从而通过门读出第一位单元的输出。

公开(公告)号：US20050047236A1

公开(公告)日：2005-03-03

申请号：US10928366

申请日：2004-08-30

申请人： Masanori Shirahama ,  Masashi Agata ,  Toshiaki Kawasaki ,  Ryuji Nishihara

发明人： Masanori Shirahama ,  Masashi Agata ,  Toshiaki Kawasaki ,  Ryuji Nishihara

IPC分类号： G11C16/02 ,  G11C7/06 ,  G11C7/10 ,  G11C16/06 ,  G11C7/00 ,  G11C29/00

CPC分类号： G11C7/1096 ,  G11C7/062 ,  G11C7/1078

摘要： A semiconductor integrated circuit device includes: first and second nonvolatile memory elements; a first amplifier for amplifying an output signal from the first nonvolatile memory element to output the amplified signal; and a second amplifier for outputting to the first amplifier a control signal generated by amplifying an output signal from the second nonvolatile memory element. The second amplifier fixes the output signal from the first amplifier at a high potential or a low potential based on data stored in the second nonvolatile memory element.

摘要翻译： 一种半导体集成电路器件，包括：第一和第二非易失性存储元件; 第一放大器，用于放大来自第一非易失性存储器元件的输出信号以输出放大的信号; 以及第二放大器，用于向第一放大器输出通过放大来自第二非易失性存储元件的输出信号而产生的控制信号。 第二放大器基于存储在第二非易失性存储器元件中的数据，将来自第一放大器的输出信号固定在高电位或低电位。

公开(公告)号：US06788565B2

公开(公告)日：2004-09-07

申请号：US10394262

申请日：2003-03-24

申请人： Masashi Agata ,  Kazunari Takahashi ,  Masanori Shirahama ,  Naoki Kuroda ,  Hiroyuki Sadakata ,  Ryuji Nishihara

发明人： Masashi Agata ,  Kazunari Takahashi ,  Masanori Shirahama ,  Naoki Kuroda ,  Hiroyuki Sadakata ,  Ryuji Nishihara

IPC分类号： G11C1140

CPC分类号： G11C11/405 ,  H01L27/108

摘要： A semiconductor memory device has a plurality of memory cells each having a first transistor, a second transistor having a source or drain connected to one portion of the source or drain of the first transistor, and a third transistor having a source or drain connected to the other portion of the source or drain of the first transistor. The first transistor accumulates, in the channel thereof, charges transferred from the second and third transistors.

摘要翻译： 半导体存储器件具有多个存储单元，每个存储单元具有第一晶体管，第二晶体管具有连接到第一晶体管的源极或漏极的一部分的源极或漏极;以及第三晶体管，源极或漏极连接到第一晶体管， 第一晶体管的源极或漏极的另一部分。 第一晶体管在其通道中累积从第二和第三晶体管传送的电荷。

公开(公告)号：US6137713A

公开(公告)日：2000-10-24

申请号：US420576

申请日：1999-10-19

申请人： Naoki Kuroda ,  Masashi Agata ,  Kazunari Takahashi

发明人： Naoki Kuroda ,  Masashi Agata ,  Kazunari Takahashi

IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C11/24 ,  G11C11/405 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/108 ,  G11C11/24 ,  G11C11/405 ,  G11C5/02 ,  G11C5/063 ,  H01L27/10885

摘要： Over an active region with two bent portions on a semiconductor substrate, first and second word lines extend to cross these bent portions and to be vertically spaced apart from each other. Around at the center of the active region, a capacitor for storing data thereon and a capacitor contact are formed. A first bit line contact, which is connected to the active region, is formed on the opposite side to the capacitor contact across the first word line over the active region. A second bit line contact, which is also connected to the active region, is formed on the opposite side to the capacitor contact across the second word line over the active region. These first and second bit line contacts are provided substantially symmetrically about the center of the memory cell. In a pair of memory cells adjacent to each other along bit lines, one vertical end of the active region in one of the memory cells is continuous with an associated vertical end of the active region in the other memory cell. And each of the first and second bit line contacts is shared between an adjacent pair of memory cells.

摘要翻译： 在半导体衬底上具有两个弯曲部分的有源区域上，第一和第二字线延伸以跨越这些弯曲部分并且彼此垂直间隔开。 在有源区域的中心附近形成用于存储数据的电容器和电容器触点。 连接到有源区域的第一位线触点形成在跨过有源区域的跨第一字线的电容器触点的相反侧。 还连接到有源区的第二位线触点形成在跨过有源区的跨越第二字线的电容器触点的相反侧。 这些第一和第二位线触点基本上围绕存储器单元的中心对称地设置。 在沿着位线彼此相邻的一对存储单元中，一个存储单元中的有源区的一个垂直端与另一个存储单元中的有源区的相关联的垂直端连续。 并且第一和第二位线触点中的每一个在相邻的一对存储单元之间共享。

公开(公告)号：US5892384A

公开(公告)日：1999-04-06

申请号：US658931

申请日：1996-05-31

申请人： Toshio Yamada ,  Masashi Agata

发明人： Toshio Yamada ,  Masashi Agata

IPC分类号： G11C7/00 ,  G06F1/04 ,  G06F1/06 ,  G06F1/10 ,  G11C11/407 ,  G11C11/4076 ,  H03K3/02 ,  H03K3/10 ,  H03K5/13 ,  H03K5/131 ,  H03K5/19 ,  H04L7/00 ,  H03H11/26

CPC分类号： G06F1/04 ,  G06F1/10 ,  H03K5/131 ,  H03K5/133 ,  H03K5/135 ,  H03K2005/00052 ,  H03K2005/00286

摘要： A timing signal generation circuit according to the present invention includes: a delay circuit for transmitting an input clock signal while delaying the clock signal, the delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the delay circuit; a detection delay circuit for transmitting the clock signal while delaying the clock signal, the detection delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the detection delay circuit; a plurality of sample/hold circuits each having a sampling signal terminal, the sampling signal terminals being connected to corresponding ones of the plurality of intermediate taps of the detection delay circuit; a plurality of boundary delay circuits for detecting an edge of the clock signal, the boundary detection circuits being connected to respective output terminals of the sample/hold circuits; and an output selection circuit for extracting the clock signal via at least one of the plurality of intermediate taps selected in accordance with an edge position of the clock signal detected by the boundary detection circuits, the output selection circuit outputting the extracted clock signal as a timing signal.